SLG505YC256C
Clock Synthesizer for Intel
PCI-Express Gen2 Chipset
Features
Output Summary
•
SLG505YC256C is fully compliant to Intel CK505 clock
specification revision 1.0
•
2- differential CPU clock outputs @ 0.8V
•
1 - selectable differential CPU/SRC clock output @ 0.8V
•
SRC clocks compliant to PCI-Express Gen2 reference
clock requirement (except SRC_0 and SRC_1)
•
1 - selectable differential DOT96/SRC clock output @ 0.8V
•
TME (Trusted Mode Enable) input to disable over-clocking
support
•
6 - differential Serial Reference Clock (SRC) clock outputs
@ 0.8V
•
Two programmable single-ended outputs - 25MHz for LAN
PHY with Wake-on-LAN support and 24.576MHz for
1394A controller
•
1 - selectable differential SATA/SRC clock output @ 0.8V
•
1 - single-ended 48MHz clock output @ 3.3V
•
6 - single-ended 33MHz clock outputs @ 3.3V
•
3.3 and low voltage (0.8V) I/O Power Supply
•
1 - single-ended 14.318MHz clock output @ 3.3V
•
Available in both commercial and industrial temperature
ranges
56 pin TSSOP Package
•
Pin Configuration
Table 1. Frequency Select Table (FS_C, FS_B, FS_A)
F
S
_
C
F
S
_
B
F
S
_
A
CPU
(MHz)
SRC
(MHz)
PCI
(MHz)
REF
(MHz)
DOT_
96
(MHz)
USB
(MHz)
0
0
0
266.6
100.0
33.3
14.318
96.0
48.0
PCI_0/CLKREQ_A#
1
56
SCL
VDD_PCI
2
55
SDA
PCI_1/CLKREQ_B#
3
54
REF/FS_C/TEST_SEL
TME/PCI_2
4
53
VDD_REF
0
0
1
133.3
100.0
33.3
14.318
96.0
48.0
0
1
0
200.0
100.0
33.3
14.318
96.0
48.0
CFG_0/PCI_3
5
52
XTAL_IN
6
51
XTAL_OUT
7
50
VSS_REF
8 1
9
49
FS_B/TEST_MODE
0
1
1
166.6
100.0
33.3
14.318
96.0
48.0
PCI_4/SRC_5_EN
1
0
0
333.3
100.0
33.3
14.318
96.0
48.0
PCIF_5/ITP_EN
1
0
1
100.0
100.0
33.3
14.318
96.0
48.0
VSS_PCI
1
1
0
400.0
100.0
33.3
14.318
96.0
48.0
1
1
1
Reserved
VDD_48
USB/FS_A
11
VDD_I/O
12
SRC_0/DOT_96
B
1
b
4
B
1
b
3
B
1
b
2
B
1
b
1
Pin 17
Pin 18
0
0
0
0
SRC_1
SRC_1#
0
0
0
1
SRC_1
(LCD_CLK Stdby)
SRC_1#
(LCD_CLK Stdby)
PROG_SE_1
PROG_SE_2
0
0
1
0
LCD_CLK (-0.5% SS)
LCD_CLK# (-0.5% SS)
0
0
1
1
LCD_CLK (-1.0% SS)
LCD_CLK# (-1.0% SS)
13
SRC_0#/DOT_96#
14
VSS_I/O
15
VDD_PLL3
16
CKPWRGD/PD#
47
SLG505YC256C
VSS_48
Table 2. PROG_SE_1 and PROG_SE_2 Configuration
48
10
VDD_CPU
46
CPU_0
45
CPU_0#
44
VSS_CPU
43
CPU_1_AMT
42
CPU_1_AMT#
41
VDD_CPU_I/O
SRC_1/PROG_SE_1
17
40
I/O_Vout
SRC_1#/PROG_SE_2
18
39
SRC_8/CPU_ITP
VSS_PLL3
19
38
SRC_8#/CPU_ITP#
VDD_PLL3_I/O
20
37
VDD_SRC_I/O
0
1
0
0
LCD_CLK (-1.5% SS)
LCD_CLK# (-1.5% SS)
0
1
0
1
LCD_CLK (-2.0% SS)
LCD_CLK# (-2.0% SS)
SRC_2/SATA
21
36
SRC_7/CLKREQ_F#
LCD_CLK# (-2.5% SS)
SRC_2#/SATA#
22
35
SRC_7#/CLKREQ_E#
0
1
1
0
0
1
1
1
LCD_CLK (-2.5% SS)
VSS_SRC
23
34
VSS_SRC
1
0
0
0
24.576MHz
24.576MHz
SRC_3/CLKREQ_C#
0
0
1
24.576MHz
98.304MHz
SRC_3#/CLKREQ_D#
33
32
SRC_6
1
24
25
1
0
1
0
98.304MHz
98.304MHz
VDD_SRC_I/O
26
31
VDD_SRC
1
0
1
1
27MHz
27MHz
SRC_4
27
30
PCI_STOP#/SRC_5
1
1
0
0
25MHz
25MHz
1
1
0
1
25MHz (Free-running)
24.576MHz
SRC_4#
28
29
CPU_STOP#/SRC_5#
1
1
1
0
25MHz (Free-running)
25MHz
1
1
1
1
Reserved
Reserved
SRC_6#
56-pin TSSOP
Other brands and names may be claimed as the property of others
Silego Technology, Inc.
000-0084505C-10
Downloaded from DatasheetLib.com - datasheet search engine
Rev 1.0
Revised October 20, 2009