PRELIMINARY DATA SHEET
2G bits DDR3 SDRAM
EDJ2108DEBG-MQ (256M words 8 bits, 2133Mbps)
EDJ2116DEBG-MQ (128M words 16 bits, 2133Mbps)
EDJ2108DEBG-JQ (256M words 8 bits, 1866Mbps)
EDJ2116DEBG-JQ (128M words 16 bits, 1866Mbps)
Specifications
Features
Density: 2G bits
Organization:
32M words 8 bits 8 banks (EDJ2108DEBG)
16M words 16 bits 8 banks (EDJ2116DEBG)
Package:
78-ball FBGA (EDJ2108DEBG)
96-ball FBGA (EDJ2116DEBG)
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD, VDDQ 1.5V 0.075V
Data rate
2133Mbps/1866Mbps (max.)
1KB page size (EDJ2108DEBG)
Row address: A0 to A14
Column address: A0 to A9
2KB page size (EDJ2116DEBG)
Row address: A0 to A13
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_15
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
Burst type (BT):
Sequential (8, 4 with BC)
Interleave (8, 4 with BC)
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 12
/CAS Write Latency (CWL): 5, 6, 7, 8, 9
No support CL13, CWL10
Precharge: auto precharge option for each burst
access
Driver strength: RZQ/7, RZQ/6, RZQ/5 (RZQ = 240)
Refresh: auto-refresh, self-refresh
Double-data-rate architecture: two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern
read out
ZQ calibration for DQ drive and ODT
/RESET pin for Power-up sequence and reset
function
SRT range:
Normal/extended
Programmable Output driver impedance control
Refresh cycles
Average refresh period
7.8s at 0C TC 85C
3.9s at 85C TC 95C
Operating case temperature range
TC = 0C to +95C
Document No. E1751E20 (Ver. 2.0)
Date Published January 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2011-2012