SN54F00, SN74F00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SDFS035A – MARCH 1987 – REVISED OCTOBER 1993
•
SN54F00 . . . J PACKAGE
SN74F00 . . . D OR N PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
1A
1B
1Y
2A
2B
2Y
GND
description
These devices contain four independent 2-input
NAND gates. They perform the Boolean functions
Y = A • B or Y = A + B in positive logic.
The SN54F00 is characterized for operation over
the full military temperature range of – 55°C to
125°C. The SN74F00 is characterized for
operation from 0°C to 70°C.
B
H
H
X
H
X
L
1Y
NC
2A
NC
2B
L
L
H
1B
2A
2B
3A
3B
4A
4B
1
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
logic symbol†
1A
13
1B
1A
NC
VCC
4B
OUTPUT
Y
A
14
2
SN54F00 . . . FK PACKAGE
(TOP VIEW)
FUNCTION TABLE
(each gate)
INPUTS
1
3
&
2
4
6
5
1Y
NC – No internal connection
2Y
9
8
10
3Y
12
11
13
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
1A
1B
2A
2B
3A
3B
4A
4B
1
2
3
1Y
4
5
6
2Y
9
10
8
3Y
12
13
11
4Y
Pin numbers shown are for the D, J, and N packages.
Copyright © 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–3
