MC10117
Dual 2-Wide 2-3-Input
OR-AND/OR-AND Gate
T h e M C 1 0 11 7 i s a d u a l 2 – w i d e 2 – 3 – i n p u t
OR–AND/OR–AND–Invert gate. This general purpose logic element
is designed for use in data control, such as digital multiplexing or data
distribution. Pin 9 is common to both gates.
• PD = 100 mW typ/pkg (No Load)
• tpd = 2.3 ns typ
• tr, tf = 2.2 ns typ (20%–80%)
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
LOGIC DIAGRAM
4
MC10117L
AWLYYWW
1
5
3
16
2
6
PDIP–16
P SUFFIX
CASE 648
7
9
MC10117P
AWLYYWW
1
1
10
11
14
PLCC–20
FN SUFFIX
CASE 775
15
12
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
13
A
WL
YY
WW
DIP
PIN ASSIGNMENT
VCC1
1
16
VCC2
AOUT
2
15
BOUT
AOUT
3
14
BOUT
A1IN
4
13
5
12
B1IN
A2IN
6
11
B2IN
A2IN
7
10
B2IN
VEE
8
9
= Assembly Location
= Wafer Lot
= Year
= Work Week
B1IN
A1IN
10117
AWLYYWW
A2IN, B2IN
ORDERING INFORMATION
Device
Package
Shipping
MC10117L
CDIP–16
25 Units / Rail
MC10117P
PDIP–16
25 Units / Rail
MC10117FN
PLCC–20
46 Units / Rail
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
© Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Publication Order Number:
MC10117/D