MC10211
Dual 3-Input/3-Output NOR
Gate
The MC10211 is designed to drive up to six transmission lines
simul– taneously. The multiple outputs of this device also allow the
wire “OR”–ing of several levels of gating for minimization of gate and
package count.
The ability to control three parallel lines with minimum propagation
delay from a single point makes the MC10211 particularly useful in
clock distribution applications where minimum clock skew is desired.
• PD = 160 mW typ/pkg (No Loads)
• tpd = 1.5 ns typ (All Output Loaded)
• tr, tf = 1.5 ns typ (20%–80%)
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
LOGIC DIAGRAM
16
2
PDIP–16
P SUFFIX
CASE 648
3
4
5
6
7
MC10211L
AWLYYWW
MC10211P
AWLYYWW
1
12
1
13
14
9
10
11
PLCC–20
FN SUFFIX
CASE 775
VCC1 = PIN 1, 15
VCC2 = PIN 16
VEE = PIN 8
A
WL
YY
WW
DIP
PIN ASSIGNMENT
VCC1
1
16
2
15
VCC1
AOUT
3
14
BOUT
AOUT
4
13
BOUT
AIN
5
12
AIN
6
AIN
VEE
= Assembly Location
= Wafer Lot
= Year
= Work Week
VCC2
AOUT
10211
AWLYYWW
ORDERING INFORMATION
Device
Package
Shipping
MC10211L
CDIP–16
25 Units / Rail
BOUT
MC10211P
PDIP–16
25 Units / Rail
11
BIN
MC10211FN
PLCC–20
46 Units / Rail
7
10
BIN
8
9
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 6
423
Publication Order Number:
MC10211/D