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74ACTQ32PC
54ACTQ 74ACTQ32 Quiet Series Quad 2-Input OR Gate General Description Features The ’ACTQ32 contains four 2-input OR gates and utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance FACT Quiet SeriesTM features GTOTM output control and undershoot corrector in addition to a split ground bus for superior ACMOS performance Y Y Y Y Y Y Y Logic Symbol ICC reduced by 50% Guaranteed simultaneous switching noise level and dynamic threshold performance Improved latch-up immunity Minimum 4 kV ESD protection Outputs source sink 24 mA ’ACTQ32 has TTL-compatible inputs Standard Military Drawing (SMD) ’ACTQ32 5962-89736 Connection Diagrams Pin Assignment for DIP Flatpak and SOIC IEEE IEC TL F 10893–1 Pin Assignment for LCC TL F 10893 – 2 TL F 10893 – 3 Pin Names Description An Bn On Inputs Outputs FACTTM FACT Quiet SeriesTM and GTOTM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 10893 RRD-B30M75 Printed in U S A 54ACTQ 74ACTQ32 Quiet Series Quad 2-Input OR Gate March 1993 DC Characteristics for ’ACTQ Family Devices (Continued) 74ACTQ Symbol Parameter 54ACTQ 74ACTQ TA e a 25 C VCC (V) TA e b 55 C to a 125 C TA e b 40 C to a 85 C Typ ICCT Maximum ICC Input IOLD Minimum Dynamic Output Current IOHD 55 Units Conditions Guaranteed Limits 06 16 15 mA VI e VCC b 2 1V 55 50 75 mA VOLD e 1 65V Max 55 b 50 b 75 mA VOHD e 3 85V Min 40 0 20 0 mA VIN e VCC or GND (Note 1) ICC Maximum Quiescent Supply Current 55 VOLP Quiet Output Maximum Dynamic VOL 50 11 15 V Figures 2-12 13 (Notes 2 3) VOLV Quiet Output Minimum Dynamic VOL 50 b0 6 b1 2 V Figures 2-12 13 (Notes 2 3) VIHD Minimum High Level Dynamic Input Voltage 50 19 22 V VILD Maximum Low Level Dynamic Input Voltage 50 12 08 V 20 (Notes 2 4) (Notes 2 4) Maximum test duration 2 0 ms one output loaded at a time Note 1 ICC for 54ACTQ 25 C is identical to 74ACTQ Note 2 Plastic DIP package 25 C Note 3 Max number of outputs defined as (n) Data inputs are 0V to 3V One output GND Note 4 Max number of data inputs (n) switching (n b 1) inputs switching 0V to 3V (’ACTQ) Input-under-test switching 3V to threshold (VILD) 0V to threshold (VIHD) f e 1 MHz AC Electrical Characteristics 74ACTQ Symbol 74ACTQ TA e a 25 C CL e 50 pF VCC (V) Parameter 54ACTQ TA e b55 C to a 125 C CL e 50 pF TA e b40 C to a 85 C CL e 50 pF Units Min Typ Max Min Max Min Max 50 25 60 65 15 75 25 70 ns Propagation Delay Data to Output 50 25 60 65 15 75 25 70 ns Output to Output Skew 50 05 10 10 ns tPLH Propagation Delay Data to Output tPHL tOSHL tOSLH Voltage Range 5 0 is 5 0V g 0 5V Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device The specification applies to any outputs switching in the same direction either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH) Parameter guaranteed by design Capacitance Parameter Typ Units Conditions CIN Symbol Input Capacitance 45 pF VCC e OPEN CPD Power Dissipation Capacitance 68 pF VCC e 5 0V 3
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