74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Rev. 03 — 14 March 2008
Product data sheet
1. General description
The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with
JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with
complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
2. Features
I
I
I
I
Asynchronous 8-bit parallel load
Synchronous serial input
Complies with JEDEC standard no. 7A
ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Applications
I Parallel-to-serial data conversion
74HC165; 74HCT165
NXP Semiconductors
8-bit parallel-in/serial out shift register
11 12 13 14 3
4
5
6
D0 D1 D2 D3 D4 D5 D6 D7
1 PL
10 DS
2 CP
15 CE
Q7 9
8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT
Q7 7
mna992
Fig 3.
Functional diagram
6. Pinning information
6.1 Pinning
74HC165
74HCT165
PL
terminal 1
index area
16 VCC
74HC165
74HCT165
1
16 VCC
CP
2
15 CE
CP
2
15 CE
D4
3
14 D3
D4
3
14 D3
D5
4
13 D2
D5
4
13 D2
D6
5
12 D1
D7
6
Q7
7
6
11 D0
Q7
7
10 DS
GND
8
9
GND(1)
Q7
11 D0
10 DS
9
D7
Q7
12 D1
8
5
GND
D6
1
PL
001aah565
Transparent top view
001aah564
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 4.
Pin configuration (DIP16, SO16
and (T)SSOP16)
Fig 5.
Pin configuration (DHVQFN16)
74HC_HCT165_3
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 03 — 14 March 2008
3 of 22