CY7C199C
256K (32K x 8) Static RAM
Features
General Description
• Fast access time: 12 ns
The CY7C199C is a high-performance CMOS Asynchronous
SRAM organized as 32K by 8 bits that supports an
asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected.
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL–compatible Inputs and Outputs
See the Truth Table in this data sheet for a complete
description of read and write modes
• 2.0V Data Retention
• Low CMOS standby power
• Automated Power-down when deselected
• Available in Pb-free and non Pb-free 28-pin (300-Mil)
Molded SOJ, 28-pin (300-Mil) DIP and 28-pin TSOP I
packages
Logic Block Diagram
32K x 8
RAM Array
ARRAY
Sense Amps
Row Decoder
Input Buffer
I/Ox
CE
Column Decoder
WE
Power
Down
Circuit
OE
X
A
X
Product Portfolio
12 ns
15 ns
20 ns
Maximum Access Time
12
15
20
ns
Maximum Operating Current
85
80
75
mA
Maximum CMOS Standby Current (L)
500
Unit
µA
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05408 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
