MC10H109
Dual 4-5-Input OR/NOR
Gate
The MC10H109 is a dual 4–5–input OR/NOR gate. This MECL
10H part is a functional/pinout duplication of the standard MECL 10K
family part, with 100% improvement in propagation delay, and no
increase in power–supply current.
• Propagation Delay, 1.0 ns Typical
• Power Dissipation 35 mW/Gate Typical (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
MC10H109L
AWLYYWW
1
LOGIC DIAGRAM
4
5
16
PDIP–16
P SUFFIX
CASE 648
3
6
7
9
10
11
12
13
2
MC10H109P
AWLYYWW
1
1
PLCC–20
FN SUFFIX
CASE 775
14
15
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
A
WL
YY
WW
DIP
PIN ASSIGNMENT
10H109
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
1
16
AOUT
2
15
3
14
4
13
AIN
5
12
6
11
7
10
8
9
46 Units/Rail
BIN
VEE
PLCC–20
BIN
AIN
25 Units/Rail
BIN
AIN
PDIP–16
MC10H109FN
BIN
25 Units/Rail
BOUT
AIN
CDIP–16
BOUT
AOUT
Shipping
MC10H109L
VCC2
Package
MC10H109P
VCC1
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 6
1
Publication Order Number:
MC10H109/D