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by MCM6206BB/D
SEMICONDUCTOR TECHNICAL DATA
MCM6206BB
Product Preview
32K x 8 Bit Fast Static RAM
The MCM6206BB is a 262,144 bit static random access memory organized as
32,768 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes, while CMOS circuitry reduces power consumption and provides
for greater reliability.
This device meets JEDEC standards for functionality and pinout, and is available in plastic small–outline J–leaded packages.
•
•
•
•
•
Single 5 V ± 10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
Fast Access Times: 12/15/20/25 ns
Equal Address and Chip Enable Access Times
Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
• Low Power Operation: 125 – 140 mA Maximum AC
• Fully TTL Compatible — Three State Output
J PACKAGE
300 MIL SOJ
CASE
810B–03
PIN ASSIGNMENT
A
A
A
A
6
23
A
7
22
G
8
21
A
A
9
20
E
A
10
19
DQ
DQ
11
18
DQ
12
17
DQ
DQ
MEMORY MATRIX
24
13
16
DQ
VSS
ROW
DECODER
A
5
DQ
A
25
A
VSS
A
4
A
A
26
A
VCC
W
3
A
A
V CC
27
A
A
28
2
A
BLOCK DIAGRAM
1
A
14
15
DQ
A
A
PIN NAMES
A
DQ
INPUT
DATA
CONTROL
DQ
E
W
G
.
.
.
A . . . . . . . . . . . . . . . . . . . . Address Input
DQ . . . . . . . . . . Data Input/Data Output
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
VCC . . . . . . . . . . . Power Supply (+ 5 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
COLUMN I/O
COLUMN DECODER
A
A
A
A
A
A
CIRCUIT
CONTROL
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
6/4/97
© Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM6206BB
1
