HY57V281620HC(L/S)T
4 Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V281620HC(L/S)T is organized as 4banks of 2,097,152x16
HY57V281620HC(L/S)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.3±0.3V power supply
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4, 8 or Full page for Sequential Burst
•
Data mask function by UDQM or LDQM
•
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency ; 2, 3 Clocks
Internal four banks operation
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V281620HCT-6
166MHz
HY57V281620HCT-7
143MHz
HY57V281620HCT-K
133MHz
HY57V281620HCT-H
133MHz
HY57V281620HCT-8
125MHz
HY57V281620HCT-P
100MHz
HY57V281620HCT-S
100MHz
HY57V281620HC(L/S)T-6
166MHz
HY57V281620HC(L/S)T-7
143MHz
HY57V281620HC(L/S)T-K
133MHz
HY57V281620HC(L/S)T-H
133MHz
HY57V281620HC(L/S)T-8
125MHz
HY57V281620HC(L/S)T-P
100MHz
HY57V281620HC(L/S)T-S
Power
Organization
Interface
Package
4Banks x 2Mbits
x16
LVTTL
400mil 54pin TSOP II
100MHz
Normal
Low power
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.3/Mar. 02
2
