CMOS SuperSync FIFO™
8,192 x 18
16,384 x 18
FEATURES
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Choose among the following memory organizations:
IDT72255LA
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8,192 x 18
IDT72265LA
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16,384 x 18
Pin-compatible with the IDT72275/72285 SuperSync FIFOs
10ns read/write cycle time (8ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Retransmit operation with fixed, low first word data latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing
simultaneously)
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IDT72255LA
IDT72265LA
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64pin Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION
The IDT72255LA/72265LA are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls. These
FIFOs offer numerous improvements over previous SuperSync FIFOs,
including the following:
• The limitation of the frequency of one clock input with respect to the other has
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
FUNCTIONAL BLOCK DIAGRAM
WEN
D0 -D17
WCLK
INPUT REGISTER
L D SEN
OFFSET REGISTER
FLAG
LOGIC
WRITE CONTROL
LOGIC
RAM ARRAY
8,192 x 18
16,384 x 18
WRITE POINTER
F F /IR
PAF
EF /OR
P AE
HF
FWFT/SI
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
P RS
RESET
LOGIC
RCLK
REN
OE
Q0 -Q17
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SuperSync FIFO is a trademark of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
4670 drw01
OCTOBER 2005
1
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4670/2
