KM44C1005D
CMOS DRAM
1M x 4bit CMOS Quad CAS DRAM with Extended Data Out
DESCRIPTION
This is a family of 1,048,576 x 4bit Extended Data Out Quad CAS CMOS DRAMs. Extended Data Out offers high speed random access
of memory cells within the same row. Access time (-5, -6 or -7), power consumption(Normal), and package type (SOJ or TSOP-II) are
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in Low power version. Four seperate CAS pins provide for seperate I/O operation allowing
this device to operate in parity mode. This 1Mx4 Extended Data Out DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.
• Extended Data Out mode operation
(Fast Page Mode with Extended data out)
FEATURES
• Four seperate CAS pins provide for seperate I/O
• Part Identification
operation
• CAS-before-RAS refresh capability
- KM44C1005D(5V, 1K Ref.)
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• Active Power Dissipation
• TTL compatible inputs and outputs
Unit : mW
Speed
Active power dissipation
-5
468
-6
413
-7
• Early Write or output enable controlled write
358
• JEDEC Standard pinout
• Available in 26(24)-pin SOJ 300mil and TSOP(II)
300mil packages
• Single +5V±10% power supply
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
Refresh
cycle
Refresh Period
KM44C1005D
1K
16ms
Normal
RAS
CAS0~3
W
Control
Clocks
Refresh Timer
• Performance Range
Speed
tRAC
tCAC
-5
50ns
-6
60ns
-7
70ns
Row Decoder
Refresh Control
tRC
tHPC
15ns
84ns
20ns
15ns
104ns
25ns
20ns
124ns
30ns
Refresh Counter
Memory Array
1,048,576 x 4
Cells
Row Address Buffer
A0~A9
Col. Address Buffer
Vcc
Vss
VBB Generator
Column Decoder
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sense Amps & I/O
Part
NO.
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
OE
