PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
Features
Description
• PLL clock distribution optimized for SSTL_2 DDR SDRAM
applications.
• Distributes one differential clock input pair to five differential
clock output pairs.
• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
• External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the input clocks.
• Operates at AVDD = 2.5V for core circuit and internal PLL,
and VDDQ = 2.5V for differential output drivers
• Packaging (Pb-free & Green available):
– 28-pin TSSOP (L)
PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM
applications. This PLL Clock Buffer is designed for 2.5 VDDQ and
2.5V AVDD operation and differential data input and output levels.
The device is a zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to five differential pairs of clock outputs
(Y[0:4], Y[0:4]) and one differential pair feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the
Analog Power input (AVDD). When the AVDD is strapped low, the
PLL is turned off and bypassed for test purposes.
Block Diagram
Pin Configuration
The PI6CV855 is able to track Spread Spectrum Clocking to reduce
EMI.
GND
1
28
Y4
Y0
2
27
Y0
Y0
3
26
Y1
Y4
VDDQ
VDDQ
4
25
GND
Y1
CLK
5
24
FBOUT
23
22
FBOUT
VDDQ
Y3
CLK
AVDD
AGND
6
8
21
FBIN
Y3
GND
9
20
FBIN
Y4
Y1
10
19
Y4
Y1
11
18
GND
VDDQ
FBOUT
VDDQ
12
17
Y3
FBOUT
Y2
13
16
Y3
Y2
14
15
GND
Y0
CLK
CLK
PLL
FBIN
Y2
Y2
FBIN
Logic
and
Test Ciruit
AVDD
08-0298
1
7
28-Pin
L
PS8545D
11/12/08
