1Gb: x4, x8, x16 DDR SDRAM
Features
Double Data Rate (DDR) SDRAM
MT46V256M4 – 64 Meg x 4 x 4 banks
MT46V128M8 – 32 Meg x 8 x 4 banks
MT46V64M16 – 16 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets
Features
Options
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
VDD = VDDQ = +2.6V ±0.1V (DDR400)
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two
–one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
• tRAS lockout supported (tRAP = tRCD)
• Configuration
256 Meg x 4 (64 Meg x 4 x 4 banks)
128 Meg x 8 (32 Meg x 8 x 4 banks)
64 Meg x 16 (16 Meg x 16 x 4 banks)1
• Plastic Package – OCPL
66-pin TSOP(400 mil width, 0.65mm
pin pitch)
66-pin TSOP lead-free (400 mil width,
0.65mm pin pitch)
• Timing – Cycle Time
7.5ns @ CL = 2.5 (DDR266B)2
6ns @ CL = 2.5 (DDR333B)2
5ns @ CL = 3 (DDR400B)
• Temperature Rating
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
• Design Revision
Table 1:
Marking
256M4
128M8
64M16
TG
P
-75
-6T
-5B
None
IT
:A
Notes:1. Contact Micron for product availability.
2. See Table 3 on page 2 for module compatibility.
Addressing Configuration
256 Meg x 4
Table 2:
64 Meg x 16
64 Meg x 4 x 4 banks
8K
16K (A0–A13)
4(BA0,BA1)
4K(A0–A9, A11, A12)
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
128 Meg x 8
32 Meg x 8 x 4 banks
8K
16K (A0–A13)
4(BA0,BA1)
2K(A0–A9, A11)
16 Meg x 16 x 4 banks
8K
16K (A0–A13)
4(BA0,BA1)
1K(A0–A9)
Key Timing Parameters
CL = CAS (read) latency; data out window is minimum clock rate at CL = 2.5
Clock Rate
Speed Grade
CL = 2
CL = 2.5
CL = 3
Data-Out
Window
Access
Window
DQS–DQ
Skew
-75
-6T
-5B
100 MHz
133 MHz
133 MHz
133 MHz
167 MHz
167 MHz
NA
NA
200 MHz
2.5ns
2.0ns
1.6ns
±0.75ns
±0.70ns
±0.70ns
+0.50ns
+0.45ns
+0.40ns
PDF: 09005aef80a2f898/Source: 09005aef80a2f8ae
1gbBDDRx4x8x16_1.fm - Rev. D 1/06 EN
1
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©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
