Wor
ld's
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est &
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SPLD t
ispGAL22V10AV/B/C
In-System Programmable Low Voltage
´®
E2CMOS PLD Generic Array Logic
December 2008
Data Sheet
Features
Introduction
■ High Performance
The ispGAL22V10A is manufactured using Lattice
Semiconductor’s advanced E2CMOS process, which
combines CMOS with Electrically Erasable (E2) floating
gate technology. With an advanced E2 low-power cell
and full CMOS logic approach, the ispGAL22V10A family offers fast pin-to-pin speeds, while simultaneously
delivering low standby power without requiring any
“turbo bits” or other traditional power management
schemes. The ispGAL22V10A can interface with both
3.3V, 2.5V and 1.8V signal levels.
• tPD = 2.3ns propagation delay
• fMAX = 455 MHz maximum operating frequency
• tCO = 2ns maximum from clock input to data
output
• tSU = 1.3 ns clock set-up time
■ Low Power
• 1.8V core E2CMOS® technology
• Typical standby power <300µW
(ispGAL22V10AC)
• CMOS design techniques provide low static and
dynamic power
The ispGAL22V10A is functionally compatible with the
ispGAL22LV10, GAL22LV10 and GAL22V10.
■ Space-Saving Packaging
Figure 1. Functional Block Diagram
• Available in 32-pin QFNS (Quad Flat-pack,
No lead, Saw-singulated) package 5mm x 5mm
body size1
8
■ Easy System Integration
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
I
• Operation with 3.3V (ispGAL22V10AV), 2.5V
(ispGAL22V10AB) or 1.8V (ispGAL22V10AC)
supplies
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3 interface
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Lead-free package option
• Programmable output slew rate
• 3.3V PCI compatible
10
I
12
I
I
I
I
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V in-system programmable
(ISP™) using IEEE 1532 compliant interface
I
■ E2 CELL TECHNOLOGY
PROGRAMMABLE
AND-ARRAY
(132X44)
I
■ In-System Programmable
14
16
16
14
12
I
• In-system programmable logic
• 100% tested/100% yields
• High speed electrical erasure (<50ms)
I
■ Applications Include
•
•
•
•
RESET
I/CLK
I
DMA control
State machine control
High speed graphics processing
Software-driven hardware configuration
TDO
TDI
TMS
TCK
10
8
PROGRAMMING
LOGIC
PRESET
■ Boundary Scan USERCODE Register
• Supports electronic signature
1. Use 32-pin QFNS package for all new designs. Refer to PCN
#13A-08 for 32-pin QFN package discontinuance.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
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isp22v10a_03.0
