Revision 18
DS0097
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
Advanced I/O
High Capacity
• 15 K to 1 M System Gates
• Up to 144 Kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM®-enabled ProASIC®3 devices)
via JTAG (IEEE 1532–compliant)†
• FlashLock® to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
• 1 Kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
• M1 ProASIC3 Devices—ARM®Cortex®-M1 Soft Processor
Available with or without Debug
ProASIC3 Devices
A3P0151
A3P030
A3P060 A3P125
A3P250
A3P400
A3P600
2
Cortex-M1 Devices
M1A3P250 M1A3P400
M1A3P600
System Gates
15,000
30,000
60,000 125,000
250,000
400,000
600,000
Typical Equivalent Macrocells
128
256
512
1,024
2,048
–
–
VersaTiles (D-flip-flops)
384
768
1,536
3,072
6,144
9,216
13,824
RAM Kbits (1,024 bits)
–
–
18
36
36
54
108
4,608-Bit Blocks
–
–
4
8
8
12
24
FlashROM Kbits
1
1
1
1
1
1
1
Secure (AES) ISP 3
–
–
Yes
Yes
Yes
Yes
Yes
Integrated PLL in CCCs
–
–
1
1
1
1
1
VersaNet Globals 4
6
6
18
18
18
18
18
I/O Banks
2
2
2
2
4
4
4
Maximum User I/Os
49
81
96
133
157
194
235
Notes:
1. A3P015 is not recommended for new designs.
2. Refer to the Cortex-M1 product brief for more information.
3. AES is not available for Cortex-M1 ProASIC3 devices.
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.
5. The M1A3P250 device does not support this package.
6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet.
7. Package not available.
† A3P015 and A3P030 devices do not support this feature.
March 2016
© 2016 Microsemi Corporation
A3P1000
M1A3P1000
1,000,000
–
24,576
144
32
1
Yes
1
18
4
300
‡ Supported only by A3P015 and A3P030 devices.
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