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ISPLSI1016EA-100LT44

製品説明
仕様・特性

ispLSI 1016EA ® In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, One Dedicated Input — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Functionally Compatible with ispLSI 1016E • NEW FEATURES — 100% IEEE 1149.1 Boundary Scan Testable — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User-Selectable 3.3V or 5V I/O Supports MixedVoltage Systems (VCCIO Pin) — Open-Drain Output Option B7 D Q A2 Logic A3 Array B6 B5 D Q D Q GLB B4 B3 A4 D Q EW Output Routing Pool A0 A1 Output Routing Pool Features A5 A6 Global Routing Pool (GRP) pM 5V AC H D 4 ES A IG 5 F N O S R N A7 B2 B1 B0 CLK E2CMOS® TECHNOLOGY • HIGH-PERFORMANCE — fmax = 200 MHz Maximum Operating Frequency — tpd = 4.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power 0139C/1016EA Description The ispLSI 1016EA is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, one Dedicated Input pin, two Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016EA features 5V in-system programmability (ISP™) and in-system diagnostic capabilities via an IEEE 1149.1 Test Access Port. The ispLSI 1016EA offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1016 architecture, the ispLSI 1016EA device adds user-selectable 3.3V or 5V I/O and open-drain output options. • IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Device for Faster Prototyping SE is • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity U The basic unit of logic on the ispLSI 1016EA device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (Figure 1). There are a total of 16 GLBs in the ispLSI 1016EA device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and a dedicated input. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2007 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 1016ea_02.1 1 April 2007

ブランド

LATTICE

会社名

Lattice Semiconductor Corporation

本社国名

U.S.A

事業概要

主力製品は、FPGA(Field-Programmable Gate Array)、CPLD(Complex Programmable Logic Device)、プログラマブルパワーマネジメント製品である。 FPGAの世界シェアはザイリンクス、アルテラに次いで第3位である。 半導体ベンダーのため、自社で生産ラインは保有していない。製造は富士通セミコンダクターなどで行っている。

供給状況

 
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