ESMT
SDRAM
M12L128168A (2N)
2M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
Burst Read single write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
ORDERING INFORMATION
Product ID
Max
Freq.
Package
Comments
M12L128168A-5TG2N
200MHz 54 Pin TSOPII
Pb-free
M12L128168A-5BG2N
200MHz
54 Ball FBGA
Pb-free
M12L128168A-6TG2N
166MHz 54 Pin TSOPII
Pb-free
M12L128168A-6BG2N
166MHz
54 Ball FBGA
Pb-free
M12L128168A-7TG2N
143MHz 54 Pin TSOPII
Pb-free
M12L128168A-7BG2N
143MHz
Pb-free
54 Ball FBGA
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
PIN CONFIGURATION (TOP VIEW)
BALL CONFIGURATION (TOP VIEW)
(TSOPII 54L, 400milX875mil Body, 0.8mm Pin Pitch)
(BGA 54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.1
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