HD74HC240
Octal Buffers/Line Drivers/Line Receivers
(with inverted 3-state outputs)
REJ03D0594–0200
(Previous ADE-205-471)
Rev.2.00
Jan 31, 2006
Description
The HD74HC240 is an inverting buffer and has two active low enables (1G and 2G). Each enable independently
controls 4 buffers. This device does not have schmitt trigger inputs.
Features
•
•
•
•
•
•
High Speed Operation: tpd = 10 ns typ (CL = 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74HC240P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
P
—
HD74HC240FPEL
SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
EL (2,000 pcs/reel)
PRSP0020DC-A
RP
(FP-20DBV)
PTSP0020JB-A
HD74HC240TELL
TSSOP-20 pin
T
(TTP-20DAV)
Note: Please consult the sales office for the above package availability.
HD74HC240RPEL
SOP-20 pin (JEDEC)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
G
H
L
L
H
L
X
Z
:
:
:
:
high level
low level
irrelevant
off (high-impedance) state of a 3-state output
Rev.2.00 Jan 31, 2006 page 1 of 7
A
X
H
L
Output
Y
Z
L
H
