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部品型式

EL1881CS

製品説明
仕様・特性

EL1881 ® Data Sheet September 15, 2011 FN7018.2 Sync Separator, Low Power Features The EL1881 video sync separator is manufactured using Elantec’s high performance analog CMOS process. This device extracts sync timing information from both standard and non-standard video input. It provides composite sync, vertical sync, burst/back porch timing, and odd/even field detection. Fixed 70mV sync tip slicing provides sync edge detection when the video input level is between 0.5VP-P and -2VP-P (sync tip amplitude 143mV to 572mV). A single external resistor sets all internal timing to adjust for various video standards. The composite sync output follows video in sync pulses and a vertical sync pulse is output on the rising edge of the first vertical serration following the vertical pre-equalizing string. For non-standard vertical inputs, a default vertical pulse is output when the vertical signal stays low for longer than the vertical sync default delay time. The odd/even output indicates field polarity detected during the vertical blanking interval. The EL1881 is plug-in compatible with the industry-standard LM1881 and can be substituted for that part in 5V applications with lower required supply current. • NTSC, PAL, SECAM, non-standard video sync separation The EL1881 is available in the 8 Ld PDIP and SOIC packages and is specified for operation over the full -40°C to +85°C temperature range • Fixed 70mV slicing of video input levels from 0.5VP-P to 2VP-P • Low supply current - 1.5mA typ. • Single +5V supply • Composite, vertical sync output • Odd/even field output • Burst/back porch output • Available in 8 Ld PDIP and SOIC packages • Pb-free available (RoHS Compliant) Applications • Video amplifiers • PCMCIA applications • A/D drivers • Line drivers • Portable computers • High-speed communications • RGB applications Pinout • Broadcast equipment EL1881 (8 LD PDIP, SOIC) TOP VIEW COMPOSITE SYNC OUT 1 8 • Active filtering Demo Board VDD 5V COMPOSITE VIDEO IN 2 7 ODD/EVEN OUTPUT VERTICAL SYNC OUT 3 6 GND A dedicated demo board is available. RSET 5 BUST/BACK PORCH OUTPUT 4 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2004, 2011. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL1881 Absolute Maximum Ratings (TA = +25°C) Thermal Information VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Thermal Resistance (Typical, Note 5) θJA (°C/W) 8 Lead PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 to 120 Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications VDD = 5V, TA = +25°C, RSET = 681kΩ, unless otherwise specified. PARAMETER DESCRIPTION MIN TYP MAX UNIT IDD, Quiescent VDD = 5V 0.75 1.5 3 mA Clamp Voltage Pin 2, ILOAD = -100µA 1.35 1.5 1.65 V Clamp Discharge Current Pin 2 = 2V 6 12 16 µA Clamp Charge Current Pin 2 = 1V -1.3 -1 0.7 mA RSET Pin Reference Voltage Pin 6 1.1 1.22 1.35 V VOL Output Low Voltage IOL = 1.6mA 0.24 0.5 V VOH Output High Voltage IOH = -40µA 4 4.8 V IOH = -1.6mA 3 4.6 V MIN TYP MAX UNIT Dynamic Specifications PARAMETER DESCRIPTION Comp Sync Prop Delay, tCS See Figure 20 20 35 75 ns Vertical Sync Width, tVS Normal or Default Trigger, 50% to 50% 190 230 300 µs Vertical Sync Default Delay, tVSD See Figure 21 35 62 85 µs Burst/Back Porch Delay, tBD See Figure 20 120 200 300 ns Burst/Back Porch Width, tB See Figure 20 2.5 3.5 4.5 µs Input Dynamic Range Video Input Amplitude to Maintain 50% Slice Spec 0.5 2 VP-P Slice Level VSLICE/VCLAMP 55 85 mV 3 70 FN7018.2 September 15, 2011

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ELANTEC

供給状況

 
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データシート
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提携先在庫情報

型式 数量 D/C・lead 備考 選択
EL1881CS 88個    
EL1881CS 48個    
EL1881CS 3個    
EL1881CSZ 951個    
EL1881CSZ 409個    
EL1881CSZT7 2827個    
EL1881CSZT7 2000個    
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