EP7309 Data Sheet
FEATURES
High-performance,
Low-power, System-on-chip
with Enhanced
Digital Audio Interface
■ ARM720T Processor
— ARM7TDMI CPU
— 8 KB of four-way set-associative cache
— MMU with 64-entry TLB
— Thumb code support enabled
■ Ultra low power
— 90 mW at 74 MHz typical
— 30 mW at 18 MHz typical
— 10 mW in the Idle State
— <1 mW in the Standby State
■ Advanced audio decoder/decompression capability
— Supports bit streams with adaptive bit rates
— Allows for support of multiple audio decompression
algorithms (MP3, WMA, AAC, ADPCM, Audible,
etc.)
OVERVIEW
The Maverick™ EP7309 is designed for ultra-low-power
applications such as digital music players, internet appliances,
smart cellular phones or any hand-held device that features the
added capability of digital audio decompression. The corelogic functionality of the device is built around an ARM720T
processor with 8 KB of four-way set-associative unified cache
and a write buffer. Incorporated into the ARM720T is an
enhanced memory management unit (MMU) which allows for
support of sophisticated operating systems like Microsoft®
Windows® CE and Linux®.
(cont.)
(cont.)
BLOCK DIAGRAM
Digital
Audio
Interface
SERIAL PORTS
Clocks &
Timers
ICE-JTAG
Power
Management
Interrupts,
PWM & GPIO
ARM720T
ARM7TDMI CPU Core
(2) UARTs
w/ IrDA
8 KB
Write
Cache
Buffer
MMU
Boot
ROM
Bus
Bridge
Keypad&
Touch
Screen I/F
Internal Data Bus
MaverickKeyTM
SRAM &
FLASH I/F
On-chip SRAM
48 KB
USER INTERFACE
Serial
Interface
EPB Bus
LCD
Controller
MEMORY AND STORAGE
©Copyright Cirrus Logic, Inc. 2005
http://www.cirrus.com
(All Rights Reserved)
AUG ‘05
DS507F1
EP7309
High-Performance, Low-Power System on Chip
Table of Contents
FEATURES...................................................................................................................................................................1
OVERVIEW ..................................................................................................................................................................1
Processor Core - ARM720T ..................................................................................................................................6
Power Management ..............................................................................................................................................6
MaverickKey™ Unique ID ......................................................................................................................................6
Memory Interfaces .................................................................................................................................................6
Digital Audio Capability .........................................................................................................................................6
Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................6
Digital Audio Interface (DAI) ..................................................................................................................................7
CODEC Interface ..................................................................................................................................................7
SSI2 Interface ........................................................................................................................................................7
Synchronous Serial Interface ................................................................................................................................8
LCD Controller .......................................................................................................................................................8
Interrupt Controller ................................................................................................................................................8
Real-Time Clock ....................................................................................................................................................8
PLL and Clocking ..................................................................................................................................................9
DC-to-DC converter interface (PWM) ....................................................................................................................9
Timers ...................................................................................................................................................................9
General Purpose Input/Output (GPIO) ..................................................................................................................9
Hardware debug Interface .....................................................................................................................................9
Internal Boot ROM ...............................................................................................................................................10
Packaging ............................................................................................................................................................10
Pin Multiplexing ...................................................................................................................................................10
System Design ....................................................................................................................................................11
ELECTRICAL SPECIFICATIONS ......................................................................................................12
Absolute Maximum Ratings .................................................................................................................................12
Recommended Operating Conditions .................................................................................................................12
DC Characteristics ..............................................................................................................................................12
Timings ...............................................................................................................................................14
Timing Diagram Conventions ....................................................................................................................14
Timing Conditions ......................................................................................................................................14
Static Memory .....................................................................................................................................................15
Static Memory Single Read Cycle .............................................................................................................16
Static Memory Single Write Cycle .............................................................................................................17
Static Memory Burst Read Cycle ...............................................................................................................18
Static Memory Burst Write Cycle ...............................................................................................................19
SSI1 Interface ......................................................................................................................................................20
SSI2 Interface ......................................................................................................................................................21
LCD Interface ......................................................................................................................................................22
JTAG Interface .....................................................................................................................................................23
Packages ............................................................................................................................................24
208-Pin LQFP Package Characteristics ..............................................................................................................24
208-Pin LQFP Package Specifications ......................................................................................................24
208-Pin LQFP Pin Diagram .......................................................................................................................25
208-Pin LQFP Numeric Pin Listing ............................................................................................................26
204-Ball TFBGA Package Characteristics ...........................................................................................................29
204-Ball TFBGA Package Specifications ..................................................................................................29
204-Ball TFBGA Pinout (Top View) ...........................................................................................................30
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
3