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FAN8404D
August 1989 DP8402A DP8403 DP8404 DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC’s) General Description The DP8402A DP8403 DP8404 and DP8405 devices are 32-bit parallel error detection and correction circuits (EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404 and DP8405 600-mil packages The EDACs use a modified Hamming code to generate a 7-bit check word from a 32-bit data word This check word is stored along with the data word during the memory write cycle During the memory read cycle the 39-bit words from memory are processed by the EDACs to determine if errors have occurred in memory Single-bit errors in the 32-bit data word are flagged and corrected Single-bit errors in the 7-bit check word are flagged and the CPU sends the EDAC through the correction cycle even though the 32-bit data word is not in error The correction cycle will simply pass along the original 32-bit data word in this case and produce error syndrome bits to pinpoint the error-generating location Double bit errors are flagged but not corrected These errors may occur in any two bits of the 39-bit word from memory (two errors in the 32-bit data word two errors in the 7-bit check word or one error in each word) The gross-error condition of all lows or all highs from memory will be detected Otherwise errors in three or more bits of the 39-bit word are beyond the capabilities of these devices to detect Read-modify-write (byte-control) operations can be performed with the DP8402A and DP8403 EDACs by using output latch enable LEDBO and the individual OEB0 thru OEB3 byte control pins Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read the contents of the DB and CB input latches These will determine if the failure occurred in memory or in the EDAC Features Y Y Y Y Y Y Detects and corrects single-bit errors Detects and flags double-bit errors Built-in diagnostic capability Fast write and read cycle processing times Byte-write capability DP8402A and DP8403 Fully pin and function compatible with TI’s SN74ALS632A thru SN74ALS635 series System Environment TL F 8535 – 1 TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 8535 RRD-B30M105 Printed in U S A DP8402A DP8403 DP8404 DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC’s) PRELIMINARY Mode Definitions PCC Pin Definitions DP8402A MODE PIN NAME DESCRIPTION S1 S0 MODE OPERATION 0 L L WRITE Input dataword and output checkword 1 L H DIAGNOSTICS Input various data words against latched checkword output valid error flags 2 H L READ FLAG Input dataword and output error flags 3 H H CORRECT Latched input data and checkword output corrected data and syndrome code Pin Definitions S0 S1 Control of EDAC mode see preceding Mode Definitions DB0 thru DB31 I O port for 32 bit dataword CB0 thru CB6 I O port for 7 bit checkword Also output port for the syndrome error code during error correction mode OEB0 thru Dataword output buffer enable When high OEB3 output buffers are at TRI-STATE Each pin (DP8402A controls 8 I O ports OEB0 controls DB0 DP8403) thru DB7 OEB1 controls DB8 thru DB15 OEB2 controls DB16 thru DB23 and OEB3 controls DB24 thru DB31 LEDBO Data word output Latch enable When high (DP8402A it inhibits input to the Latch Operates on all DP8403) 32 bits of the dataword OEDB TRI-STATE control for the data I O port (DP8404 When high output buffers are at DP8405) TRI-STATE OECB Checkword output buffer enable When high the output buffers are in TRI-STATE mode ERR Single error output flag a low indicates at least a single bit error MERR Multiple error output flag a low indicates two or more errors present pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VCC LEDBO MERR ERR DB0 DB1 DB2 NC NC NC DB3 DB4 DB5 OEBO DB6 DB7 GND GND DB8 DB9 OEB1 DB10 DB11 DB12 DB13 DB14 NC NC NC DB15 NC CB6 CB5 CB4 pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 OECB CB3 CB2 CB1 CB0 DB16 DB17 NC NC DB18 DB19 DB20 DB21 OEB2 DB22 DB23 GND GND DB24 DB25 OEB3 DB26 DB27 DB28 NC NC NC NC DB29 DB30 DB31 S0 S1 VCC TABLE I Write Control Function Memory Cycle EDAC Function Write Generate check word Control S1 S0 L Data I O DB Control OEBn or OEDB DB Output Latch DP8402A DP8403 LEDBO Check I O CB Control OECB Input H X Output check bits L L Error Flags ERR MERR H H See Table II for details on check bit generation Memory Write Cycle Details 2 These seven check bits are stored in memory along with the original 32-bit data word This 32-bit word will later be used in the memory read cycle for error detection and correction During a memory write cycle the check bits (CB0 thru CB6) are generated internally in the EDAC by seven 16-input parity generators using the 32-bit data word as defined in Table 3
FAIRCHILD
Fairchild Semiconductor International, Inc
U.S.A
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