ACEX 1K
®
Programmable Logic Device Family
May 2003, ver. 3.4
Features...
Data Sheet
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Table 1. ACEXTM 1K Device Features
Feature
EP1K10
EP1K30
EP1K50
EP1K100
Typical gates
10,000
30,000
50,000
100,000
Maximum system gates
56,000
119,000
199,000
257,000
576
1,728
2,880
4,992
3
6
10
12
12,288
24,576
40,960
49,152
136
171
249
333
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
Altera Corporation
DS-ACEX-3.4
1
13
Development
Tools
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Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
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Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
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Dual-port capability with up to 16-bit width per embedded array
block (EAB)
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Logic array for general logic functions
High density
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10,000 to 100,000 typical gates (see Table 1)
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Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
Cost-efficient programmable architecture for high-volume
applications
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Cost-optimized process
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Low cost solution for high-performance communications
applications
System-level features
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MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
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Low power consumption
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Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MHz
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Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Extended temperature range
