CY7C4201V/4211V/4221VCY7C4241V/4251VLow Voltage 256/512/1K/4K/8K x 9 Synchronous FIFOs
CY7C4201V/4211V/4221V
CY7C4241V/4251V
Low Voltage 256/512/1K/4K/8K x 9 Synchronous FIFOs
Features
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High-speed, low-power, first-in, first-out (FIFO) memories
❐ 256 x 9 (CY7C4201V)
❐ 512 x 9 (CY7C4211V)
❐ 1K x 9 (CY7C4221V)
❐ 4K x 9 (CY7C4241V)
❐ 8K x 9 (CY7C4251V)
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High-speed 66-MHz operation (15-ns read/write cycle time)
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Low power (ICC = 20 mA)
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3.3V operation for low power consumption and easy integration
into low-voltage systems
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5V-tolerant inputs VIH max = 5V
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Fully asynchronous and simultaneous read and write operation
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Empty, Full, and Programmable Almost Empty and
Almost Full status flags
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TTL compatible
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Output Enable (OE) pin
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Independent read and write enable pins
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Center power and ground pins for reduced noise
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Width expansion capability
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Space saving 32-pin 7 mm × 7 mm TQFP
32-pin PLCC
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Available in Pb-Free Packages
Functional Description
The CY7C42X1V are high-speed, low-power, FIFO memories
with clocked read and write interfaces. All are nine bits wide.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is controlled
by a Free-Running Clock (WCLK) and two Write Enable pins
(WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written into
the FIFO on the rising edge of the WCLK signal. While WEN1,
WEN2/LD is held active, data is continually written into the FIFO
on each WCLK cycle. The output port is controlled in a similar
manner by a Free-Running Read Clock (RCLK) and two Read
Enable Pins (REN1, REN2). In addition, the CY7C42X1V has an
Output Enable Pin (OE). The Read (RCLK) and Write (WCLK)
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write
applications. Clock frequencies up to 66 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic to
direct the flow of data.
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 38-06010 Rev. *C
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198 Champion Court
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San Jose, CA 95134-1709
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408-943-2600
Revised March 19, 2010
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