2Gb: x16, x32 Mobile LPDDR SDRAM
Features
Mobile Low-Power DDR SDRAM
MT46H128M16LF – 32 Meg x 16 x 4 Banks
MT46H64M32LF – 16 Meg x 32 x 4 Banks
MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2
MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4
MT46H256M32R4 – 32 Meg x 16 x 4 Banks x 4
Features
Options
Marking
-5
200 MHz
5.0ns
-54
185 MHz
5.0ns
• VDD/VDDQ
– 1.8V/1.8V
• Configuration
– 128 Meg x 16 (32 Meg x 16 x 4
banks)
– 64 Meg x 32 (16 Meg x 32 x 4
banks)
• Addressing
– JEDEC-standard
– Reduced page-size1
– 4-die stack reduced page-size2
– 2-die stack standard
– 4-die stack standard
• Plastic "green" package
– 60-ball VFBGA (10mm x 11.5mm) 3
– 90-ball VFBGA (10mm x 13mm) 4
• PoP (plastic "green" package)
– 168-ball VFBGA (12mm x 12mm) 4
– 168-ball WFBGA (12mm x 12mm) 4
– 168-ball WFBGA (12mm x 12mm) 4
– 240-ball WFBGA (14mm x 14mm) 4
• Timing – cycle time
– 5ns @ CL = 3 (200 MHz)
– 5.4ns @ CL = 3 (185 MHz)
– 6ns @ CL = 3 (166 MHz)
– 7.5ns @ CL = 3 (133 MHz)
• Power
– Standard IDD2/IDD6
• Operating temperature range
– Commercial (0˚ to +70˚C)
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)1
• Design revision
-6
166 MHz
5.0ns
Notes:
-75
133 MHz
6.0ns
• VDD/VDDQ = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data; one mask
per byte
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh (TCSR)
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh; 32ms for the automotive temperature
range
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
Clock Rate
Access Time
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
1
1.
2.
3.
4.
H
128M16
64M32
LF
LG
R4
L2
L4
CK
CM
JV
KQ
MA
MC
-5
-54
-6
-75
None
None
IT
AT
:A
Contact factory for availability.
Available in the 168-ball JV package only.
Available only for x16 configuration.
Available only for x32 configuration.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
