1Gb: x16, x32 Mobile LPDDR SDRAM
Features
Mobile Low-Power DDR SDRAM
MT46H64M16LF – 16 Meg x 16 x 4 Banks
MT46H32M32LF – 8 Meg x 32 x 4 Banks
Features
Options
• VDD/VDDQ
– 1.8V/1.8V
• Configuration
– 64 Meg x 16 (16 Meg x 16 x 4 banks)
– 32 Meg x 32 (8 Meg x 32 x 4 banks)
• Row-size option
– JEDEC-standard option
– Reduced page-size option1
• Plastic green package
– 60-ball VFBGA (10mm x 11.5mm)2
– 90-ball VFBGA (10mm x 13mm)3
• Timing – cycle time
– 5ns @ CL = 3
– 5.4ns @ CL = 3
– 6ns @ CL = 3
– 7.5ns @ CL = 3
• Power
– Standard IDD2/IDD6
– Low-power IDD2/IDD6
• Operating temperature range
– Commercial (0˚ to +70˚C)
– Industrial (–40˚C to +85˚C)
• Design revision
• VDD/VDDQ = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data—one mask
per byte
• Programmable burst lengths (BL): 2, 4, 8, or 161
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• On-chip temp sensor to control self refresh rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh
Notes:
Marking
H
64M16
32M32
LF
LG
CK
CM
-5
-54
-6
-75
None
L
None
IT
:A
1. Contact factory for availability.
2. Only available for x16 configuration.
3. Only available for x32 configuration.
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
Clock Rate (MHz)
Access Time
-5
200
5.0ns
-54
185
5.0ns
-6
166
5.5ns
-75
133
6.0ns
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
1
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© 2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
