PEEL™ 18CV8 -7/-10/-15/-25
CMOS Programmable Electrically Erasable Logic Device
Features
Architectural Flexibility
- Enhanced architecture fits in more logic
- 74 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear
- Independent output enables
- 20 Pin DIP/SOIC/TSSOP and PLCC
Multiple Speed Power, Temperature Options
- VCC = 5 Volts ±10%
- Speeds ranging from 7ns to 25 ns
- Power as low as 37mA at 25MHz
- Commercial and industrial versions available
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Development / Programmer Support
- Third party software and programmers
- WinPLACE Development Software
- PLD-to-PEEL™ JEDEC file translator
Application Versatility
- Replaces random logic
- Super sets PLDs (PAL, GAL, EPLD)
- Enhanced Architecture fits more logic than ordinary PLDs
General Description
The PEEL™18CV8 is a Programmable Electrically Erasable
Logic (PEEL™) device providing an attractive alternative to
ordinary PLDs. The PEEL™18CV8 offers the performance, flexibility, ease of design and production practicality needed by logic
designers today.
The PEEL™18CV8 architecture allows it to replace over 20 standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also provides additional architecture features so more logic can be put into every
design. Anachip’s JEDEC file translator instantly converts to the
PEEL™18CV8 existing 20-pin PLDs without the need to rework
the existing design. Development and programming support for the
PEEL™18CV8 is provided by popular third-party program- mers
and development software.
The PEEL™18CV8 is available in 20-pin DIP, PLCC, SOIC and
TSSOP packages with speeds ranging from 7ns to 25ns with
power consumption as low as 37mA. EE-Reprogrammability
provides the convenience of instant reprogramming for development and reusable production inventory minimizing the impact of
programming changes or errors. EE-Reprogrammability also
improves factory testability, thus assuring the highest quality possible.
Figure 3 Block Diagram
Figure 2 Pin Configuration
I/CLK
1
20
VCC
I
2
19
I/O
I
3
18
I/O
I
4
17
I/O
I
5
16
I/O
I
6
15
I/O
I
7
14
I/O
I
8
13
I/O
I
9
12
I/O
GND
10
11
I
DIP
TSSOP
PLCC
™
SOIC
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
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