Low Skew, 1-to-2, Differential/LVCMOSto-0.7V HCSL Fanout Buffer
ICS85102I
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The ICS85102I is a low skew, high performance 1-to-2 Differential-to-HCSL fanout buffer. The ICS85102I has a differential
clock input. The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during
asynchronous assertion/deassertion of the clock enable pin.
• Two 0.7V differential HCSL outputs
• Selectable differential CLK0, nCLK0 or LVCMOS inputs
• CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
• CLK1 can accept the following input levels:
LVCMOS or LVTTL
Guaranteed output and par t-to-par t skew characteristics
make the ICS85102I ideal for those applications demanding
well defined performance and repeatability.
• Maximum output frequency: 500MHz
• Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
• Output skew: 65ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Propagation delay: 3.2ns (maximum)
• Additive phase jitter, RMS: 0.14ps typical @ 250MHz
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
CLK_EN Pullup
PIN ASSIGNMENT
CLK_EN
CLK_SEL
CLK0
nCLK0
CLK1
nc
nc
IREF
D
Q
CLK0 Pulldown
nCLK0 Pullup/Pulldown
CLK1 Pulldown
LE
0
Q0
nQ0
1
CLK_SEL Pulldown
Q1
nQ1
16
15
14
13
12
11
10
9
GND
VDD
Q0
nQ0
Q1
nQ1
VDD
VDD
ICS85102I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm body package
G Package
Top View
IREF
ICS85102AGI REVISION A MAY 27, 2011
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©2011 Integrated Device Technology, Inc.
