HM628512C Series
4 M SRAM (512-kword × 8-bit)
ADE-203-1212C (Z)
Rev. 3.0
Aug. 5, 2002
Description
The Hitac hi HM628512C is a 4-Mbit static R AM orga nized 512-kw ord × 8-bit. It rea liz es higher density,
higher per forma nce and low powe r consumption by employing C MOS proc ess tec hnology (6- tr ansistor
memory ce ll) . The devic e, pac kage d in a 525-mil S OP (f oot print pitch width) or 400-mil TS OP TYP E II or
600-mil plastic DI P, is ava ila ble for high density mounting. The HM628512C is suita ble for batter y bac kup
system.
Features
• Single 5 V supply
• Access time: 55/70 ns (max)
• Power dissipation
Active: 10 mW/MHz (typ)
Standby: 4 µW (typ)
• Completely static memory. No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state output
• Directly TTL compatible: All inputs and outputs
• Battery backup operation
