CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
EZ-USB® FX2LP™ USB Microcontroller
High-Speed USB Peripheral Controller
EZ-USB FX2LP™ USB Microcontroller High Speed USB Peripheral Controller
Features
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USB 2.0 USB IF Hi-Speed certified (TID # 40460272)
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3.3-V operation with 5-V tolerant inputs
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Single-chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
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Vectored USB interrupts and GPIF/FIFO interrupts
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Fit-, form-, and function-compatible with the FX2
❐ Pin-compatible0
❐ Object-code-compatible
❐ Functionally compatible (FX2LP is a superset)
Separate data buffers for the setup and data portions of a
CONTROL transfer
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Integrated I2C controller; runs at 100 or 400 kHz
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Four integrated FIFOs
❐ Integrated glue logic and FIFOs lower system cost
❐ Automatic conversion to and from 16-bit buses
❐ Master or slave operation
❐ Uses external clock or asynchronous strobes
❐ Easy interface to ASIC and DSP ICs
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Available in commercial and industrial temperature grades
(all packages except VFBGA)
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Ultra-low power: ICC no more than 85 mA in any mode
❐ Ideal for bus- and battery-powered applications
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Software: 8051 code runs from:
❐ Internal RAM, which is downloaded through USB
❐ Internal RAM, which is loaded from EEPROM
❐ External memory device (128-pin package)
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16 KB of on-chip code/data RAM
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Four programmable BULK, INTERRUPT, and
ISOCHRONOUS endpoints
❐ Buffering options: Double, triple, and quad
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Features (CY7C68013A/14A only)
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CY7C68014A: Ideal for battery-powered applications
❐ Suspend current: 100 A (typ)
Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
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CY7C68013A: Ideal for nonbattery-powered applications
❐ Suspend current: 300 A (typ)
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8-bit or 16-bit external data interface
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Smart media standard ECC generation
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GPIF™ (general programmable interface)
❐ Enables direct connection to most parallel interfaces
❐ Programmable waveform descriptors and configuration
registers to define waveforms
❐ Supports multiple ready (RDY) inputs and control (CTL)
outputs
Available in five Pb-free packages with up to 40 GPIOs
❐ 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin
QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin
VFBGA (24 GPIOs)
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Integrated, industry-standard, enhanced 8051
❐ 48-MHz, 24-MHz, or 12-MHz CPU operation
❐ Four clocks per instruction cycle
❐ Two USARTs
❐ Three counter/timers
❐ Expanded interrupt system
❐ Two data pointers
Features (CY7C68015A/16A only)
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CY7C68016A: Ideal for battery-powered applications
❐ Suspend current: 100 A (typ)
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CY7C68015A: Ideal for nonbattery-powered applications
❐ Suspend current: 300 A (typ)
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Available in Pb-free 56-pin QFN package (26 GPIOs)
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Two more GPIOs than CY7C68013A/14A enabling additional
features in the same footprint
For a complete list of related resources, click here.
Errata: For information on silicon errata, see “Errata” on page 67. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-08032 Rev. *X
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198 Champion Court
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San Jose, CA 95134-1709
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408-943-2600
Revised January 15, 2015