1bCY7C185
CY7C185
8K x 8 Static RAM
Functional Description[1]
Features
• High speed
The CY7C185 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE1), an active
HIGH chip enable (CE2), and active LOW output enable (OE)
and tri-state drivers. This device has an automatic
power-down feature (CE1 or CE2), reducing the power
consumption by 70% when deselected. The CY7C185 is in a
standard 300-mil-wide DIP, SOJ, or SOIC package.
— 15 ns
• Fast tDOE
• Low active power
— 715 mW
• Low standby power
— 85 mW
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE1 and WE
inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2 and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in non Pb-free 28-pin (300-Mil) Molded SOJ,
28-pin (300-Mil) Molded SOIC and both Pb-free and non
Pb-free in 28-pin (300-Mil) Molded DIP
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
I/O0
INPUT BUFFER
I/O2
SENSE AMPS
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
I/O1
8K x 8
ARRAY
I/O3
I/O4
I/O5
I/O6
CE1
CE2
WE
COLUMN DECODER
POWER
DOWN
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O7
A12
A11
A10
A0
A9
OE
Selection Guide
-15
15
130
15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
-20
20
110
15
-25
25
100
15
-35
35
100
15
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 24, 2006
