PIC18F6525/6621/8525/8621
64/80-Pin High-Performance, 64-Kbyte Enhanced Flash
Microcontrollers with A/D
High Performance RISC CPU:
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External Memory Interface
(PIC18F8525/8621 Devices Only):
Linear program memory addressing to 64 Kbytes
Linear data memory addressing to 4 Kbytes
1 Kbyte of data EEPROM
Up to 10 MIPs operation:
- DC – 40 MHz osc./clock input
- 4 MHz – 10 MHz osc./clock input with PLL active
16-bit wide instructions, 8-bit wide data path
Priority levels for interrupts
31-level, software accessible hardware stack
8 x 8 Single-cycle Hardware Multiplier
• Address capability of up to 2 Mbytes
• 16-bit interface
Analog Features:
• 10-bit, up to 16-channel Analog-to-Digital
Converter (A/D):
- Auto-Acquisition
- Conversion available during Sleep
• Programmable 16-level Low-Voltage Detection
(LVD) module:
- Supports interrupt on Low-Voltage Detection
• Programmable Brown-out Reset (BOR)
• Dual analog comparators:
- Programmable input/output configuration
Peripheral Features:
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High current sink/source 25 mA/25 mA
Four external interrupt pins
Timer0 module: 8-bit/16-bit timer/counter
Timer1 module: 16-bit timer/counter
Timer2 module: 8-bit timer/counter
Timer3 module: 16-bit timer/counter
Timer4 module: 8-bit timer/counter
Secondary oscillator clock option – Timer1/Timer3
Two Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: 1 to 10-bit PWM resolution
Three Enhanced Capture/Compare/PWM (ECCP)
modules:
- Same Capture/Compare features as CCP
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown on external event
- Auto-Restart
Master Synchronous Serial Port (MSSP) module
with two modes of operation:
- 2/3/4-wire SPI (supports all 4 SPI modes)
- I2C™ Master and Slave mode
Two Enhanced USART modules:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-Wake-up on Start bit
- Auto-Baud Rate Detect
Parallel Slave Port (PSP) module
Program Memory
Device
Special Microcontroller Features:
• 100,000 erase/write cycle Enhanced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• 1 second programming time
• Flash/Data EEPROM Retention: > 100 years
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own On-Chip
RC Oscillator for reliable operation
• Programmable code protection
• Power-saving Sleep mode
• Selectable oscillator options including:
- 4x Phase Lock Loop (PLL) – of primary oscillator
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming™ (ICSP™) via two pins
• MPLAB® In-Circuit Debug (ICD 2) via two pins
CMOS Technology:
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Data Memory
# Single-Word SRAM EEPROM I/O
Bytes Instructions (bytes) (bytes)
10-bit
A/D
(ch)
Low power, high-speed Flash technology
Fully static design
Wide operating voltage range (2.0V to 5.5V)
Industrial and Extended temperature ranges
CCP/
MSSP/SPI™/
Timers
ECCP PWM Master I2C™ EUSART 8-bit/16-bit EMI
PIC18F6525
48K
24576
3840
1024
53
12
2/3
14
Y
2
2/3
N
PIC18F6621
64K
32768
3840
1024
53
12
2/3
14
Y
2
2/3
N
PIC18F8525
48K
24576
3840
1024
70
16
2/3
14
Y
2
2/3
Y
PIC18F8621
64K
32768
3840
1024
70
16
2/3
14
Y
2
2/3
Y
2003-2013 Microchip Technology Inc.
DS39612C-page 1
PIC18F6525/6621/8525/8621
Pin Diagrams (Cont.’d)
RJ1/OE
RJ0/ALE
RD7/AD7/PSP7
RD6/AD6/PSP6
RD5/AD5/PSP5
RD4/AD4/PSP4
RD3/AD3/PSP3
RD2/AD2/PSP2
RD1/AD1/PSP1
VSS
VDD
RD0/AD0/PSP0
RE7/AD15/ECCP2(1)/P2A(1)
RE6/AD14/P1B(2)
RE5/AD13/P1C(2)
RE4/AD12/P3B(2)
RE2/AD10/CS/P2B
RE3/AD11/P3C(2)
RH0/A16
RH1/A17
80-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/A18
RH3/A19
RE1/AD9/WR/P2C
RE0/AD8/RD/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
MCLR/VPP/RG5(3)
RG4/CCP5/P1D
VSS
VDD
RF7/SS
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15/P1B(2)
RH6/AN14/P1C(2)
1
60
2
59
58
57
56
55
3
4
5
6
7
8
9
10
11
12
13
14
15
16
54
53
52
51
50
PIC18F8525
PIC18F8621
49
48
47
46
45
44
43
42
41
17
18
19
20
RJ2/WRL
RJ3/WRH
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3/ECCP2(1)/P2A(1)
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/ECCP1/P1A
RJ7/UB
RJ6/LB
Note 1:
2:
3:
RJ5/CE
RJ4/BA0
RC7/RX1/DT1
RC6/TX1/CK1
RC0/T1OSO/T13CKI
RA4/T0CKI
RC1/T1OSI/ECCP2(1)/P2A(1)
RA5/AN4/LVDIN
VDD
VSS
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
AVSS
RA3/AN3/VREF+
AVDD
RF0/AN5
RF1/AN6/C2OUT
RH4/AN12/P3C(2)
RH5/AN13/P3B(2)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device
is configured in Microcontroller mode; or with RB3 when CCP2MX is cleared in all other program memory modes.
P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set and with RH7:RH4 when ECCPMX is
not set.
RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2003-2013 Microchip Technology Inc.
DS39612C-page 3
