HIGH-SPEED 3.3V
32/16K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features:
◆
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9/12/15ns (max.)
– Industrial: 7.5ns (max.)
Low-power operation
– IDT70V9279/69S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V9279/69L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
Flow-through or Pipelined output mode on either port via
the FT/PIPE pin
Counter enable and reset features
◆
◆
◆
◆
◆
◆
IDT70V9279/69S/L
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/WL
R/WR
UBL
UBR
CE0L
CE0R
1
0
0/1
1
0
CE1L
0/1
CE1R
LBL
OEL
LBR
OER
FT/PIPEL
0/1
1b 0bb
a 1a 0a
0a 1a
a
0b 1b
b
0/1
FT/PIPER
,
I/O8L-I/O15L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0L-I/O7L
I/O0R-I/O7R
A14R(1)
A14L(1)
A0L
CLKL
ADSL
CNTEN L
Counter/
Address
Reg.
MEMORY
ARRAY
CNTRSTL
Counter/
Address
Reg.
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3743 drw 01
NOTE:
1. A14X is a NC for IDT70V9269.
JANUARY 2006
1
©2006 Integrated Device Technology, Inc.
DSC 3743/10