®
ARCHITECTURAL OVERVIEW
S5933
FEATURES
INTRODUCTION TO THE PCI LOCAL BUS
• PCI 2.1 Master/Slave Controller
The local bus concept was developed to break the
PC data bottleneck. Traditional PC bus architectures
are inadequate to meet the demands of today’s
graphics-oriented systems and large application
sizes. A local bus moves peripherals off the I/O bus
and places them closer to the system’s processor
bus, providing faster data transfer between the processor and peripherals.
The PCI Local Bus addresses the industry’s need for
a local bus standard that is not directly dependent on
the speed and size of the processor bus, and that is
both reliable and expandable. It represents the first
time in the history of the PC industry that a common
bus, independent of microprocessor design and
manufacturer, has been adopted and used by rival
PC computer architectures. PCI offers simple “plug
and play” capability for the end user, and its performance is more than adequate for the most demanding applications, such as full-motion video.
• Generic 8/16/32-bit Add-On user bus
• Four definable memory block Pass-Thru regions
• Direct Add-On mailbox data strobe pin for PCI
interrupt
• Optional boot load/external BIOS serial or bytewide nvRAM
• Two 32 Byte FIFOs and 32 byte mailboxes
• Industry standard 160-pin PQFP
APPLICATIONS
• Digital Video
• Networking
• Multimedia
• Data Aquisition
Figure 1. S5933 Block Diagram
ADDRESS
LATCH
PASS THRU ADDRESS
PCI
BUS
ADD-ON
INTERFACE
WRITE
PASS THRU DATA
ADDR
READ
DECODER
PROGRAM–
MABLE
DECODER
MAILBOXES
SELECT &
CONTROL
BUFFER
MUX/
DEMUX
FIFO
BUFFERS & LATCHES
DATA BUS
8/16/32
CONFIG.
REGS
WRITE
READ
CONTROL
STATUS &
INTERRUPT
PCI Bus Master (DMA)Transfer Counters
BIOS ROM INTERFACE
3-9
