TC554161AFT-70,-85,-10,-70L,-85L,-10L
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT STATIC RAM
DESCRIPTION
The TC554161AFT is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16bits.
Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V ± 10%
power supply. Advanced circuit technology provides both high speed and low power at an operating current of 10
mA/MHz (typ) and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 2 mA standby
current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB ,
UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. The TC554161AFT is available in a plastic 54-pin
thin-small-outline package (TSOP).
FEATURES
·
·
·
·
·
·
Low-power dissipation
Operating: 55 mW/MHz (typical)
Single power supply voltage of 5 V ± 10%
Power down features using CE .
Data retention supply voltage of 2 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Standby Current (maximum):
·
TC554161AFT
-70,-70L
-70L,-85L,-10L
5.5 V
100 mA
50 mA
3.0 V
50 mA
25 mA
PIN ASSIGNMENT (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A4
A5
A6
A7
NC
I/O1
I/O2
VDD
GND
I/O3
I/O4
LB
OE
OP
NC
I/O5
I/O6
GND
VDD
I/O7
I/O8
A8
A9
A10
A11
A12
NC
70 ns
85 ns
100 ns
CE Access Time
·
-10,-10L
70 ns
85 ns
100 ns
OE Access Time
-70,-85,-10
-85,-85L
Access Time
TC554161AFT
NC
A3
A2
A1
A0
I/O16
I/O15
VDD
GND
I/O14
I/O13
UB
CE
OP
R/W
I/O12
I/O11
GND
VDD
I/O10
I/O9
NC
A17
A16
A15
A14
A13
Access Times (maximum):
35 ns
45 ns
50 ns
Package:
TSOP II54-P-400-0.80 (AFT) (Weight: 0.57 g typ)
PIN NAMES
A0~A17
I/O1~I/O16
Address Inputs
Data Inputs/Outputs
CE
Chip Enable
R/W
Read/Write Control
OE
Output Enable
LB , UB
Data Byte Control
VDD
Power (+5 V)
GND
Ground
NC
No Connection
OP*
Option
*: OP pin must be open of connected to GND.
(Normal pinout)
2001-08-17
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TC554161AFT-70,-85,-10,-70L,-85L,-10L
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VDD
Power Supply Voltage
4.5
5.0
5.5
V
VIH
Input High Voltage
2.2
¾
VDD + 0.3
V
VIL
Input Low Voltage
-0.3*
¾
0.8
V
VDH
Data Retention Supply Voltage
2.0
¾
5.5
V
-3.0 V when measured at a pulse width of 30 ns
*:
DC CHARACTERISTICS (Ta = 0° to 70°C, VDD = 5 V ± 10%)
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN = 0 V~VDD
¾
¾
±1.0
mA
ILO
Input Leakage
Current
Output Leakage
Current
CE = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD
¾
¾
±1.0
mA
IOH
Output High Current
VOH = 2.4 V
-1.0
¾
¾
mA
IOL
Output Low Current
VOL = 0.4 V
2.1
¾
¾
mA
tcycle = 70 ns
¾
¾
110
tcycle = 85 ns, 100 ns
¾
¾
100
tcycle = 1 ms
¾
15
¾
tcycle = 70 ns
CE = 0.2 V and R/W = VDD - 0.2 V,
IOUT = 0 mA,
tcycle = 85 ns, 100 ns
Other Input = VDD - 0.2 V/0.2 V
tcycle = 1 ms
¾
¾
100
¾
¾
90
¾
10
¾
CE = VIH
¾
¾
3
Ta = 25°C
¾
2
¾
Ta = 0~70°C
¾
¾
100
Ta = 25°C
¾
2
5
Ta = 0~70°C
¾
¾
50
IIL
CE = VIL and R/W = VIH,
IOUT = 0 mA,
Other Input = VIH/VIL
IDDO1
Operating Current
IDDO2
IDDS1
-70,-85,-10
Standby Current
IDDS2
CE = VDD - 0.2 V,
VDD = 2.0 V~5.5 V
-70L,-85L,-10L
mA
mA
mA
mA
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
TEST CONDITION
MAX
UNIT
CIN
Input Capacitance
VIN = GND
10
pF
COUT
Output Capacitance
VOUT = GND
10
pF
Note:
This parameter is periodically sampled and is not 100% tested.
2001-08-17
3/10
