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A1225A-2PQ100I

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仕様・特性

Revision 8 ACT 2 Family FPGAs Features • Up to 8,000 Gate Array Gates (20,000 PLD equivalent gates) • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL® Packages • Design Library with over 500 Macro Functions • Single-Module Sequence Functions • Wide-Input Combinatorial Functions • Up to 1,232 Programmable Logic Modules • Up to 998 Flip-Flops • Datapath Performance at 105 MHz • 16-Bit Accumulator Performance to 39 MHz • Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 50 MHz • Two High-Speed, Low-Skew Clock Networks • I/O Drive to 10 mA • Nonvolatile, User Programmable • Logic Fully Tested Prior to Shipment • 1.0 micron CMOS Technology Table 1 • ACT 2 Product Family Profile Device A1225A A1240A A1280A Gate Array Equivalent Gates 2,500 4,000 8,000 PLD Equivalent Gates 6,250 10,000 20,000 63 100 200 Capacity TTL Equivalent Package 20-Pin PAL Equivalent Packages Logic Modules 25 40 80 451 684 1,232 S-Module 231 348 624 C-Module 220 336 608 382 568 998 Horizontal Tracks/Channel 36 36 36 Vertical Tracks/Channel 15 15 15 250,000 400,000 750,000 83 104 140 16-Bit Prescaled Counters 105 MHz 100 MHz 85 MHz 16-Bit Loadable Counters 70 MHz 69 MHz 67 MHz 16-Bit Accumulators 39 MHz 38 MHz 36 MHz PG100 PL84 PQ100 VQ100 PG132 PL84 PQ144 – TQ176 – PG176 PL84 PQ160 – TQ176 CQ172 Flip-Flops (maximum) Routing Resources PLICE Antifuse Elements User I/Os (maximum) 1 Performance Packages2 CPGA PLCC PQFP VQFP TQFP CQFP – – Notes: 1. Performance is based on –2 speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2, dated 3-28-93. Any analysis is not endorsed by PREP. 2. See the "Product Plan" on page III for package availability. January 2012 © 2012 Microsemi Corporation I

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