IS42S81600D
IS42S16800D
16Meg x 8, 8Meg x16
128-MBIT SYNCHRONOUS DRAM
JULY 2008
• Clock frequency: 166, 143, 133 MHz
OVERVIEW
ISSI's 128Mb Synchronous DRAM achieves high-speed
• Fully synchronous; all signals referenced to a
positive clock edge
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
FEATURES
• Internal bank for hiding row access/precharge
• Power supply
IS42S81600D
VDDQ
VDD
3.3V 3.3V
IS42S16800D
3.3V 3.3V
IS42S81600D
IS42S16800D
4M x8x4 Banks
2M x16x4 Banks
54-pin TSOPII
54-pin TSOPII
• LVTTL interface
54-ball BGA
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
KEY TIMING PARAMETERS
• 4096 refresh cycles every 64 ms
Parameter
-6
-7
-75E
Unit
• Random column address every clock cycle
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
6
8
7
10
—
7.5
ns
ns
Clk Frequency
CAS Latency = 3
CAS Latency = 2
166
125
143
100
—
133
Mhz
Mhz
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
5.4
6.5
5.4
6.5
—
6.5
ns
ns
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Industrial Temperature Availability
• Lead-free Availability
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
07/28/08
1
