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MT48LC32M16A2P-75:C

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仕様・特性

512Mb: x4, x8, x16 SDRAM Features SDR SDRAM MT48LC128M4A2 – 32 Meg x 4 x 4 banks MT48LC64M8A2 – 16 Meg x 8 x 4 banks MT48LC32M16A2 – 8 Meg x 16 x 4 banks Features Options Marking • Configurations – 128 Meg x 4 (32 Meg x 4 x 4 banks) – 64 Meg x 8 (16 Meg x 8 x 4 banks) – 32 Meg x 16 (8 Meg x 16 x 4 banks) • Write recovery (tWR) – tWR = 2 CLK1 • Plastic package – OCPL2 – 54-pin TSOP II (400 mil) (standard) – 54-pin TSOP II (400 mil) Pb-free • Timing – cycle time – 7.5ns @ CL = 3 (PC133) – 7.5ns @ CL = 2 (PC133) • Self refresh – Standard – Low power • Operating temperature range – Commercial (0˚C to +70˚C) – Industrial (–40˚C to +85˚C) • Revision • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal, pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge and auto refresh modes • Self refresh mode • Auto refresh – 64ms, 8192-cycle refresh (commercial and industrial) • LVTTL-compatible inputs and outputs • Single 3.3V ±0.3V power supply Notes: 128M4 64M8 32M16 A2 TG P -75 -7E3 None L4 None IT :C 1. See technical note TN-48-05 on Micron's Web site. 2. Off-center parting line. 3. Available on x4 and x8 only. 4. Contact Micron for availability. Table 1: Key Timing Parameters CL = CAS (READ) latency Access Time Speed Grade Clock Frequency CL = 2 CL = 3 Setup Time Hold Time -7E 143 MHz – 5.4ns 1.5ns 0.8ns -75 133 MHz – 5.4ns 1.5ns 0.8ns -7E 133 MHz 5.4ns – 1.5ns 0.8ns -75 100 MHz 6ns – 1.5ns 0.8ns PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. Q 12/12 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

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