TigerSHARC
Embedded Processor
ADSP-TS101S
FEATURES
BENEFITS
300 MHz, 3.3 ns instruction cycle rate
6M bits of internal—on-chip—SRAM memory
19 mm × 19 mm (484-ball) or 27 mm × 27 mm
(625-ball) PBGA package
Dual computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
Dual integer ALUs, providing data addressing and pointer
manipulation
Integrated I/O includes 14-channel DMA controller, external
port, 4 link ports, SDRAM controller, programmable flag
pins, 2 timers, and timer expired pin for system integration
1149.1 IEEE compliant JTAG test access port for on-chip
emulation
On-chip arbitration for glueless multiprocessing with up to
8 TigerSHARC processors on a bus
Provides high performance Static Superscalar DSP operations, optimized for telecommunications infrastructure
and other large, demanding multiprocessor DSP
applications
Performs exceptionally well on DSP algorithm and I/O benchmarks (see benchmarks in Table 1 and Table 2)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, other DSPs (multiprocessor), and host
processors
Eases DSP programming through extremely flexible instruction set and high-level language-friendly DSP architecture
Enables scalable multiprocessing systems with low communications overhead
COMPUTATIONAL BLOCKS
SHIFTER
PROGRAM SEQUENCER
PC
IAB
ALU
BTB
INTERNAL MEMORY
DATA ADDRESS GENERATION
IRQ
INTEGER
J ALU
ADDR
FETCH
32
32
32 × 32
INTEGER
K ALU
32 × 32
MEMORY
M0
64K × 32
A
D
MEMORY
M1
64K × 32
A
D
6
JTAG PORT
MEMORY
M2
64K × 32
A
SDRAM CONTROLLER
D
MULTIPLIER
32
X
REGISTER
FILE
32 × 32
M0 ADDR
128
M0 DATA
MULTIPROCESSOR
INTERFACE
32
HOST INTERFACE
32
M1 ADDR
128
128
EXTERNAL PORT
M1 DATA
128
ADDR
INPUT FIFO
64
DAB
OUTPUT BUFFER
32
DAB
M2 ADDR
128
M2 DATA
DATA
OUTPUT FIFO
128
128
Y
REGISTER
FILE
32 × 32
I/O ADDRESS
32
CNTRL
CLUSTER BUS
ARBITER
I/O PROCESSOR
3
DMA
CONTROLLER
L0
LINK PORT
CONTROLLER
MULTIPLIER
L1
DMA ADDRESS
32
256
DMA DATA
ALU
SHIFTER
8
3
CONTROL/
STATUS/
TCBs
256
LINK
PORTS
LINK DATA
CONTROL/
STATUS/
BUFFERS
8
3
8
L2
3
L3
8
Figure 1. Functional Block Diagram
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2009 Analog Devices, Inc. All rights reserved.
