PEEL™ 22CV10A -7/-10/-15/-25
CMOS Programmable Electrically Erasable Logic Device
Features
High Speed/Low Power
- Speeds ranging from 7ns to 25ns
- Power as low as 30mA at 25MHz
Architectural Flexibility
- 132 product term X 44 input AND array
- Up to 22 inputs and 10 outputs
- Up to 12 configurations per macrocell
- Synchronous preset, asynchronous clear
- Independent output enables
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC
Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Pin and JEDEC compatible with 22V10
- Enhanced Architecture fits more logic
than ordinary PLDs
Development/Programmer Support
- Third party software and programmers
- Anachip PLACE Development Software
General Description
The PEEL™22CV10A is a Programmable Electrically Erasable Logic (PEEL™) device providing an attractive alternative to ordinary PLDs. The PEEL™22CV10A offers the
performance, flexibility, ease of design and production
practicality needed by logic designers today. The
PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP
and 28-pin PLCC packages (see Figure 1), with speeds
ranging from 7ns to 25ns and with power consumption as low
as 30mA. EE-reprogrammability provides the conve- nience
of instant reprogramming for development and a reusable
production
inventory,
minimizing
the
impact
of
programming changes or errors. EE-reprogrammability
also improves factory testability, thus ensuring the highest
quality possible. The PEEL™22CV10A is JEDEC file compatible with standard 22V10 PLDs. Eight additional configurations per macrocell (a total of 12) are also available by
using the “+” software/programming option (i.e., 22CV10A+
& 22CV10A++). The additional macrocell configurations
allow more logic to be put into every design. Programming
and development support for the PEEL™22CV10A are provided by popular third-party programmers and development software. Anachip also offers free PLACE
development software.
Figure 1. Pin Configuration
Figure 2. Block Diagram
I/CLK
1
24
VCC
I
2
23
I/O
I
3
22
I/O
I
4
21
I/O
I
5
20
I/O
I
6
19
I/O
I
7
18
I/O
I
8
17
I/O
I
9
16
I/O
I
10
15
I/O
I
11
14
I/O
GND
12
13
I
TSSOP
DIP
SOIC
PLCC
*Optional extra ground pin for
-7/I-7 speed grade.
9
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under
any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
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