MITSUBISHI
M54975P/FP
Bi-CMOS 8-BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M54975 is a semiconductor integrated circuit fabricated using
Bi-CMOS technology. It contains a serial input to serial/parallel
Clock
T→ 1
16 → O1
Serial input
output 8-bit CMOS shift register and CMOS latch as well as bipolar
S-IN → 2
15 → O2
8-bit parallel-output driver.
VCC
FEATURES
14 → O3
3
4
M54975P
Logic GND L-GND
Serial output S-OUT ← 5
q Serial input to serial/parallel output
Latch input LATCH → 6
q Cascade connections possible through serial output
13 → O4
11 → O6
EN
7
10 → O7
Driver GND P-GND
q Latch circuit included for each stage
8
9 → O8
Enable input
q Enable input for output control
Parallel outputs
12 → O5
q Low supply current .................................. ICC ≥ 10µA at standby
Outline 16P4(P)
16P2N-A(FP)
q Serial input/output level is compatible with standard CMOS
q Driver : Withstand voltage ...................................... BVCEO ≥ 30V
Large drive current ................................ (IO(max)=300mA)
q Wide operating temperature range ..................... Ta=-20 – +75°C
Using a number of M54975 units for bit expansion in series will
APPLICATION
entail connecting serial output (S-OUT) to S-IN of the next-stage
Thermal printer head dot driver, Serial-to parallel conversion, Relay
M54975.
and Solenoid driver
In parallel output, when the latch input is set to “H” and the outputcontrol input (enable input EN) is “L”, a clock pulse changing from
FUNCTION
“L” to “H” will cause the serial data input signal to appear at output
The M54975 consists of an 8-bit D-type flip-flop, the output of
O1, and the data will be shifted in order at outputs O2 – O8.
which is connected to 8 latches.
The parallel output will yield a signal that is inverted with respect to
When data is applied to the serial data input (S-IN) and a clock
the serial data input.
pulse is applied to clock input (T), an “L” to “H” change of the clock
Setting the LATCH input to “L” will prevent data from entering the
will cause the data input signals to enter the internal shift registers
latch.
and the data in the shift registers will be shifted in order.
When the EN input is set to “H”, all outputs (O1 – O8) will be set to
OFF. Since the internal logic state of the IC is uncertain at poweron time, set the EN input to “H” (and outputs O1 – O8 will set to
Parallel outputs
BLOCK DIAGRAM
O1
Power supply
O3
O4
O5
O6
O7
O8
15
14
13
12
11
10
9
VCC 4
Enable input
O2
16
EN 7
8 P-GND Driver GND
Q
Q
Q
Q
Q
Q
Q
Q
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
Latch input LATCH 6
Serial input
S-IN 2
T
Clock
T 1
3
L-GND
Logic GND
T
T
T
T
T
T
T
5 S-OUT Serial output