IDT70V28L
HIGH-SPEED 3.3V
64K x 16 DUAL-PORT
STATIC RAM
Features
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True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V28L
Active: 440mW (typ.)
Standby: 660µW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V28 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
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M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
CE0R
CE1R
OEL
OER
LBL
LBR
I/O8-15R
I/O 8-15L
I/O
Control
I/O 0-7L
BUSY L
I/O
Control
I/O0-7R
(1,2)
A15L
BUSYR
64Kx16
MEMORY
ARRAY
70V28
Address
Decoder
A0L
A15R
A0R
16
16
CE0L
CE1L
OEL
R/WL
Address
Decoder
(1,2)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
(2)
INT L
M/S
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
(1)
CE0R
CE1R
OER
R/WR
SEMR
(2)
INTR
4849 drw 01
JANUARY 2006
1
©2006 Integrated Device Technology, Inc.
DSC-4849/4
