CY2308
3.3 V Zero Delay Buffer
3.3 V Zero Delay Buffer
Features
The CY2308 has two banks of four outputs each that is controlled
by the select inputs as shown in the table Select Input Decoding
on page 3. If all output clocks are not required, Bank B is
three-stated. The input clock is directly applied to the output for
chip and system testing purposes by the select inputs.
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Zero input-output propagation delay, adjustable by capacitive
load on FBK input
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Multiple configurations, see Available CY2308 Configurations
on page 4 for more details
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Multiple low skew outputs
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Two banks of four outputs, three-stateable by two select inputs
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10 MHz to 133 MHz operating range
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75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
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Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
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3.3 V operation
The CY2308 is available in five different configurations as shown
in the table Available CY2308 Configurations on page 4.
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Industrial temperature available
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The CY2308-1 is the base part where the output frequencies
equal the reference if there is no counter in the feedback path.
The CY2308-1H is the high drive version of the -1 and rise and
fall times on this device are much faster.
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The CY2308-2 enables the user to obtain 2x and 1x frequencies
on each output bank. The exact configuration and output
frequencies depend on the user’s selection of output that drives
the feedback pin.
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The CY2308-3 enables the user to obtain 4x and 2x frequencies
on the outputs.
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The CY2308-4 enables the user to obtain 2x clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
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The CY2308-5H is a high drive version with REF/2 on both
banks.
The CY2308 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than 25 A
of current draw. The PLL shuts down in two additional cases as
shown in the table Select Input Decoding on page 3.
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
Functional Description
The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin. The PLL feedback is driven from
external FBK pin, so user has flexibility to choose any one of the
outputs as feedback input and connect it to FBK pin. The
input-to-output skew is less than 250 ps and output-to-output
skew is less than 200 ps.
Logic Block Diagram
/2
REF
PLL
FBK
MUX
/2
CLKA1
CLKA2
Extra Divider (–3, –4)
CLKA3
Extra Divider (–5H)
CLKA4
S2
Select Input
Decoding
S1
/2
CLKB1
CLKB2
CLKB3
Extra Divider (–2, –3)
Cypress Semiconductor Corporation
Document Number: 38-07146 Rev. *O
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198 Champion Court
CLKB4
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San Jose, CA 95134-1709
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408-943-2600
Revised March 13, 2014
