576Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Features
CIO RLDRAM® 2
MT49H64M9 – 64 Meg x 9 x 8 Banks
MT49H32M18 – 32 Meg x 18 x 8 Banks
MT49H16M36 – 16 Meg x 36 x 8 Banks
Features
Options1
• 533 MHz DDR operation (1.067 Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock
frequency)
• Organization
– 64 Meg x 9, 32 Meg x 18, and 16 Meg x 36 I/O
– 8 banks
• Reduced cycle time (15ns at 533 MHz)
• Nonmultiplexed addresses (address multiplexing
option available)
• SRAM-type interface
• Programmable READ latency (RL), row cycle time,
and burst sequence length
• Balanced READ and WRITE latencies in order to
optimize data bus utilization
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Differential input data clocks (DKx, DKx#)
• On-die DLL generates CK edge-aligned data and
output data clock signals
• Data valid signal (QVLD)
• 32ms refresh (16K refresh for each bank; 128K refresh
command must be issued in total each 32ms)
• 144-ball µBGA package
• HSTL I/O (1.5V or 1.8V nominal)
• 25–60 matched impedance outputs
• 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
• On-die termination (ODT) RTT
PDF: 09005aef80fe62fb/Source: 09005aef809f284b
576Mb_RLDRAM_2_CIO_D1.fm - Rev. J 10/12 EN
Marking
• Clock cycle timing
– 1.875ns @ tRC = 15ns
-18
t
– 2.5ns @ RC = 15ns
-25E
t
– 2.5ns @ RC = 20ns
-25
t
-33
– 3.3ns @ RC = 20ns
• Configuration
– 64 Meg x 9
64M9
– 32 Meg x 18
32M18
– 16 Meg x 36
16M36
• Operating temperature
– Commercial (0° to +95°C)
– Industrial (TC = –40°C to +95°C;
TA = –40°C to +85°C)
None
IT
• Package
– 144-ball µBGA
FM
– 144-ball µBGA (Pb-free)
BM
• Revision
:A/:B
Notes: 1. Not all options listed can be combined to
define an offered product. Use the part catalog search on www.micron.com for available
offerings.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
