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AM79C973BVDW
PRELIMINARY Am79C973/Am79C975 PCnet™-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY s Supports PC98/PC99 and Wired for Management baseline specifications DISTINCTIVE CHARACTERISTICS s Single-chip PCI-to-Wire Fast Ethernet controller — 32-bit glueless PCI host interface — Full OnNow support including pattern matching and link status wake-up events — Supports PCI clock frequency from DC to 33 MHz independent of network clock — Implements AMD’s patented Magic Packet™ technology for remote wake-up & power-on — Supports network operation with PCI clock from 15 MHz to 33 MHz — Magic Packet mode and the physical address loaded from EEPROM at power up without requiring PCI clock — High performance bus mastering architecture with integrated Direct Memory Access (DMA) Buffer Management Unit for low CPU and bus utilization — Supports PCI Bus Power Management Interface Specification Revision 1.1 — Supports Advanced Configuration and Power Interface (ACPI) Specification Version 1.0 — PCI specification revision 2.2 compliant — Supports PCI Subsystem/Subvendor ID/ Vendor ID programming through the EEPROM interface — Supports Network Device Class Power Management Specification Version 1.0a — Supports both PCI 5.0 V and 3.3 V signaling environments s Serial Management Interface enables remote alerting of system management events — Plug and Play compatible — Inter-IC (I2C) compliant electrical interface — Big endian and little endian byte alignments supported — System Management Bus (SMBus) compliant signaling interface and register access protocol s Fully Integrated 10/100 Mbps Physical Layer Interface (PHY) — Optional interrupt pin simplifies software interface — Conforms to IEEE 802.3 standard for 10BASE-T, 100BASE-TX, and 100BASE-FX interfaces s Large independent internal TX and RX FIFOs — Programmable FIFO watermarks for both TX and RX operations — Integrated 10BASE-T transceiver with onchip filtering — RX frame queuing for high latency PCI bus host operation — Fully integrated MLT-3 encoder/decoder for 100BASE-TX — Programmable allocation of buffer space between RX and TX queues — Provides a PECL interface for 100BASE-FX fiber implementations s EEPROM interface supports jumperless design and provides through-chip programming — Full-duplex capability for 10BASE-T and 100BASE-TX — Supports extensive programmability of device operation through EEPROM mapping — IEEE 802.3u Auto-Negotiation between 10 Mbps and 100 Mbps, half- and full-duplex operation s Supports up to 1 megabyte (Mbyte) optional Boot PROM and Flash for diskless node application s Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 and Blue Book Ethernet standards s Extensive programmable internal/external loopback capabilities s Extensive programmable LED status support This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. R f t AMD’ W b it ( d )f th l t t i f Publication# 21510 Rev: E Amendment/0 Issue Date: August 2000 ti
AMD
Advanced Micro Devices, Inc
U.S.A
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