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MT46V16M16BG-6

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仕様・特性

256Mb: x4, x8, x16 DDR SDRAM Features Double Data Rate (DDR) SDRAM MT46V64M4 – 16 Meg x 4 x 4 banks MT46V32M8 – 8 Meg x 8 x 4 banks MT46V16M16 – 4 Meg x 16 x 4 banks Features Options • VDD = 2.5V ±0.2V; VDDQ = 2.5V ±0.2V VDD = 2.6V ±0.1V; VDDQ = 2.6V ±0.1V (DDR400)1 • Bidirectional data strobe (DQS) transmitted/ received with data, that is, source-synchronous data capture (x16 has two – one per byte) • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask (DM) for masking write data (x16 has two – one per byte) • Programmable burst lengths (BL): 2, 4, or 8 • Auto refresh – 64ms, 8192-cycle • Longer-lead TSOP for improved reliability (OCPL) • 2.5V I/O (SSTL_2-compatible) • Concurrent auto precharge option supported • tRAS lockout supported (tRAP = tRCD) • Configuration 64M4 – 64 Meg x 4 (16 Meg x 4 x 4 banks) 32M8 – 32 Meg x 8 (8 Meg x 8 x 4 banks) 16M16 – 16 Meg x 16 (4 Meg x 16 x 4 banks) • Plastic package – OCPL TG – 66-pin TSOP P – 66-pin TSOP (Pb-free) • Plastic package CV – 60-ball FBGA (8mm x 12.5mm) CY – 60-ball FBGA (8mm x 12.5mm) (Pb-free) • Timing – cycle time -5B – 5ns @ CL = 3 (DDR400) -62 – 6ns @ CL = 2.5 (DDR333) FBGA only -6T2 – 6ns @ CL = 2.5 (DDR333) TSOP only • Self refresh None – Standard L – Low-power self refresh • Temperature rating None – Commercial (0C to +70C) IT – Industrial (–40C to +85C) • Revision :K4 – x4, x8, x16 :M – x4, x8, x16 Notes: 1. DDR400 devices operating at < DDR333 conditions can use VDD/VDDQ = 2.5V +0.2V. 2. Available only on Revision K. 3. Available only on Revision M. 4. Not recommended for new designs. Table 1: Marking Key Timing Parameters CL = CAS (READ) latency; MIN clock rate with 50% duty cycle at CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and CL = 3 (-5B) Clock Rate (MHz) Speed Grade CL = 2 CL = 2.5 CL = 3 Data-Out Window Access Window DQS–DQ Skew -5B -6 6T -75E/-75Z -75 133 133 133 133 100 167 167 167 133 133 200 n/a n/a n/a n/a 1.6ns 2.1ns 2.0ns 2.5ns 2.5ns ±0.70ns ±0.70ns ±0.70ns ±0.75ns ±0.75ns 0.40ns 0.40ns 0.45ns 0.50ns 0.50ns PDF: 09005aef80768abb/Source: 09005aef82a95a3a 256Mb_DDR_x4x8x16_D1.fm - 256Mb DDR: Rev. R, Core DDR: Rev. E 3/12 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

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