NB6L295
2.5V / 3.3V Dual Channel
Programmable Clock/Data
Delay with Differential
LVPECL Outputs
Multi−Level Inputs w/ Internal Termination
The NB6L295 is a Dual Channel Programmable Delay Chip
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designed primarily for Clock or Data de−skewing and timing
adjustment. The NB6L295 is versatile in that two individual variable
MARKING
delay channels, PD0 and PD1, can be configured in one of two
DIAGRAM*
24
operating modes, a Dual Delay or an Extended Delay.
1
In the Dual Delay Mode, each channel has a programmable delay
QFN−24
NB6L
MN SUFFIX
section which is designed using a matrix of gates and a chain of
295
CASE 485L
24
1
ALYWG
multiplexers. There is a fixed minimum delay of 3.2 ns per channel.
G
The Extended Delay Mode amounts to the additive delay of PD0
A
= Assembly Location
plus PD1 and is accomplished with the Serial Data Interface MSEL bit
L
= Wafer Lot
set High. This will internally cascade the output of PD0 into the input
Y
= Year
of PD1. Therefore, the Extended Delay path starts at the IN0/IN0
W
= Work Week
G
= Pb−Free Package
inputs, flows through PD0, cascades to the PD1 and outputs through
(Note: Microdot may be in either location)
Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended
*For additional marking information, refer to
Delay Mode.
Application Note AND8002/D.
The required delay is accomplished by programming each delay
channel via a 3−pin Serial Data Interface, described in the application
ORDERING INFORMATION
See detailed ordering and shipping information in the package
section. The digitally selectable delay has an increment resolution of
dimensions section on page 12 of this data sheet.
typically 11 ps with a net programmable delay range of either 0 ns to
6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the
Extended Delay Mode.
The Multi−Level Inputs can be driven directly by differential
LVPECL, LVDS or CML logic levels; or by single ended LVPECL,
LVCMOS or LVTTL. A single enable pin is available to control both
inputs. The SDI input pins are controlled by LVCMOS or LVTTL
level signals. The NB6L295 LVPECL output contains temperature
compensation circuitry. This device is offered in a 4 mm x 4 mm
24−pin QFN Pb−free package. The NB6L295 is a member of the
ECLinPS MAX™ family of high performance products.
Features
• 3 ps Typical Clock Jitter, RMS
• Input Clock Frequency > 1.5 GHz with 550 mV
• 20 ps Pk−Pk Typical Data Dependent Jitter
VOUTPP
• LVPECL, CML or LVDS Differential Input Compatible
• Input Data Rate > 2.5 Gb/s
• LVPECL, LVCMOS, LVTTL Single−Ended Input
• Programmable Delay Range: 0 ns to 6 ns per Delay
Compatible
Channel
• 3−Wire Serial Interface
• Programmable Delay Range: 0 ns to 11.2 ns for
• Input Enable/Disable
Extended Delay Mode
• Operating Range: VCC = 2.375 V to 3.6 V
• Total Delay Range: 3.2 ns to 8.8 ns per Delay Channel
• LVPECL Output Level; 780 mV Peak−to−Peak, Typical
• Total Delay Range: 6 ns to 17 ns in Extended Delay
• Internal 50 W Input Termination Provided
Mode
• −40°C to 85°C Ambient Operating Temperature
• Monotonic Delay: 11 ps Increments in 511 Steps
• 24−Pin QFN, 4 mm x 4 mm
• Linearity $20 ps, Maximum
• These are Pb−Free Devices*
• 100 ps Typical Rise and Fall Times
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2012
March, 2012 − Rev. 4
1
Publication Order Number:
NB6L295/D
