HOME在庫検索>在庫情報

部品型式

CY7B9334-270JC

製品説明
仕様・特性

CY7B9234 CY7B9334 SMPTE HOTLink® Transmitter/Receiver Features • SMPTE-259M-CD compliant along with SMPTE-259M encoder (CY7C9235) and decoder (CY7C9335) • Fibre Channel compliant • DVB-ASI compliant • RX PLL tolerant of long run length data patterns (>20 bits) • 8B/10B-coded or 10-bit unencoded • TTL synchronous I/O • No external PLL components • Triple PECL 100K serial outputs • Dual PECL 100K serial inputs • Low power: 350 mW (Tx), 650 mW (Rx) • Compatible with fiber-optic modules, coaxial cable, and twisted pair media • Built-In Self-Test • Single +5V supply • 28-pin PLCC • 0.8µ BiCMOS Functional Description HOTLink® The CY7B9234 SMPTE Transmitter and CY7B9334 SMPTE HOTLink Receiver bolt on to the SMPTE Scrambler Controller (CY7C9235) and SMPTE CY7B9234 Transmitter Logic Block Diagram RP ENN ENA SC/D (Da) D0− 7 (Db − h) SVS(Dj) Eight or ten bits of user data or protocol information are loaded into the SMPTE HOTLink transmitter and, in DVB mode, are encoded. Serial data is shifted out of the three differential positive ECL (PECL) serial ports at the bit rate (which is 10 times the byte rate). The SMPTE HOTLink receiver accepts the serial bit stream at its differential line receiver inputs and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. The bit stream is deserialized, and in DVB mode, decoded and checked for transmission errors. Recovered bytes are presented in parallel to the receiving host along with a byte rate clock. The 8B/10B encoder/decoder can be disabled in SMPTE or DVB systems that already encode or scramble the transmitted data. I/O signals are available to create a seamless interface with both asynchronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e., CY7C44X). A Built-In Self-Test pattern generator and checker allows testing of the transmitter, receiver, and the connecting link as a part of a system diagnostic check. SMPTE HOTLink devices are ideal for a variety of video applications including video transmission equipment, video recorders, video editing equipment, and video routers. CY7B9334 Receiver Logic Block Diagram RF FOTO ENABLE INPUT REGISTER CKW Descrambler/Framer Controller (CY7C9335) completing the four piece chipset to transfer uncompressed SMPTE-259M encoded video over high-speed serial links (fiber, coax, and twisted pair). SMPTE HOTLink supports SMPTE-259M-CD standard data rates at 270 and 360 Mbps. Figure 1 illustrates typical connections to host systems or controllers. FRAMER A/B INA+ INA− DATA INB (INB+) SI(INB− ) PECL TTL ENCODER SO CLOCK GENERATOR OUTA SHIFTER OUTB OUTC MODE BISTEN TEST LOGIC SHIFTER DECODER REGISTER CLOCK SYNC DECODER REFCLK MODE OUTPUT REGISTER TEST LOGIC BISTEN CKR RDY Q0− 7 (Qb − h) RVS(Qj) SC/D (Qa) Cypress Semiconductor Corporation Document #: 38-02014 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 27, 2004 [+] Feedback

ブランド

CYPRESS

会社名

Cypress Semiconductor

本社国名

U.S.A

事業概要

主力製品は、NOR型フラッシュ・メモリ、F-RAMおよびSRAM Traveoマイクロコントローラ、業界唯一のPSoCソリューション、アナログ回路、PMIC、CapSense capacitive touch-sensingコントローラ、Wireless BLE Bluetooth Low-Energy、そしてUSB connectivityソリューションである。 2015年にスパンション社と合併し、フラッシュメモリ、マイクロコントローラ、ミックスドシグナル製品およびアナログ製品も強化も行っています。

供給状況

 
Not pic File
お求めのCY7B9334-270JCは、クレバーテックの担当が在庫調査を行いメールにて見積回答致します。

「見積依頼」ボタンを押してお気軽にお問合せください。


当サイトの取引の流れ

見積依頼→在庫確認→見積回答→注文→検収→支払 となります。


お取引内容はこちら
CY7B9334-270JCの取扱い販売会社 株式会社クレバーテック  会社情報(PDF)    戻る


0.0715599060