MC14503B
Hex Non-Inverting 3-State
Buffer
The MC14503B is a hex non−inverting buffer with 3−state outputs,
and a high current source and sink capability. The 3−state outputs
make it useful in common bussing applications. Two disable controls
are provided. A high level on the Disable A input causes the outputs of
buffers 1 through 4 to go into a high impedance state and a high level
on the Disable B input causes the outputs of buffers 5 and 6 to go into
a high impedance state.
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1
SOIC−16
D SUFFIX
CASE 751B
Features
• 3−State Outputs
• TTL Compatible − Will Drive One TTL Load Over Full Temperature
•
•
•
•
•
Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Two Disable Controls for Added Versatility
Pin for Pin Replacement for MM80C97 and 340097
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
PIN ASSIGNMENT
DIS A
1
16
VDD
IN 1
2
15
DIS B
OUT 1
3
14
IN 6
IN 2
Value
−0.5 to +18.0
−0.5 to VDD
+ 0.5
Iin
±10
Iout
±25
PD
500
TA
−55 to +125
°C
−65 to +150
°C
260
°C
10
IN 4
VSS
8
9
mW
Ambient Temperature Range
7
mA
Power Dissipation, per Package (Note 2)
OUT 5
mA
Output Current (DC or Transient) per Pin
11
V
Input Current (DC or Transient) per Pin
6
OUT 4
V
Vin, Vout
IN 5
Unit
VDD
OUT 6
12
OUT 3
Symbol
13
5
IN 3
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1)
4
OUT 2
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Storage Temperature Range
Lead Temperature (8−Second Soldering)
MARKING DIAGRAM
16
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Maximum Ratings are those values beyond which damage to the device may
occur.
2. Temperature Derating:
“D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
14503BG
AWLYWW
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
TRUTH TABLE
Inn
Appropriate
Disable
Input
Outn
0
0
0
1
0
1
X
1
High
Impedance
X = Don’t Care
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 10
1
Publication Order Number:
MC14503B/D
